rinus lee | semiconductor technologist
turning science into applications
ABOUT ME
Rinus Lee
Semiconductor Technologist
Hi, I’m an electrical engineer working in the semiconductor industry, where I focus on developing process technologies for angstrom-scale manufacturing. I enjoy pushing the limits of semiconductor technology and turning scientific advances into real-world applications.
I began my career in industry after completing a PhD in Electrical Engineering at the National University of Singapore in 2009. Since then, my research has focused on novel process technologies and exploratory device concepts, resulting in 116 publications, 11 invited talks, and 29 patents that have contributed to advances in transistor scaling and semiconductor innovation.
Early in my career, I received the Marubun Research Promotion Foundation Travel Grant (2006), the TSMC Outstanding Student Research Award, Gold (2007), and the TSMC Internship Program First Prize (2008). My PhD work was further recognized with the IEEE EDS PhD Fellowship (2009) and the European MRS Young Scientist Award (2009).
In industry, my contributions have been recognized with the GlobalFoundries Invention Achievement Level Awards (2017, 2020), the Best Paper Award at the TEL US Internal Technology Forum (2023), and most recently, the TEL CEO Award (2025).
I am also passionate about giving back to the IEEE community. From 2016 to 2018, I served as Chair of the IEEE EDS Chapter in Schenectady, NY, during which our chapter was named the 2017 Chapter of the Year. I have also served on the EDS Newsletter Committee (2017–2022) and on the technical program committees for MRS Spring (2017, 2019), IEDM (2020, 2021), and EDTM (2024).
CONFERENCE PUBLICATIONS
66: Impact of Metal Underlayers on EUV Lithography Performance with Sn-Based Metal Oxide Resists
SPIE Advanced Lithography + Patterning Conference, San Jose CA, USA Feb 22 - 26, 2026
T. Miyahara, D. Hamashita, K. Imakita, J. Huang, J. Oakley, N. Okabe, K. Yamada, H. Aizawa, R. Lee
65: Ab-Initio Investigation of Fundamental Reaction Mechanisms, Environmental Effects and EUV Reactivity of Sn-Based Metal Oxide Photoresists
SPIE Advanced Lithography + Patterning Conference, San Jose CA, USA Feb 22 - 26, 2026
N. Liza, K. Yamada, A. Agawarl, I. Simms, R. Burns, T. Omatsu, R. Lee, M. Muramatsu, H. Cheng, R. Yamaguchi
64: The Systematic Study of NbOx Inter Layer for Ferroelectric Memory
IEEE Semiconductor Interface Specialist Conference, San Diego CA, USA Dec 10 -13, 2025
S. Aoki, R. Soedibyo, S. Lynch, K. Imakita, Y. Otsuki, D. O’Meara, D. Triyoso, K. Tapily, R. Lee, H. Aizawa
63: (Invited) Transfer Learning on Edge Using 14nm CMOS-compatible ReRAM Array and Analog In-memory Training Algorithm
International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 6 - 10, 2025
Takashi Ando, Omobayode Fagbohungbe, Kenichi Imakita, Hiroyuki Miyazoe, Sara Aoki, Ruturaj Pujari, Sarah Lynch, Paul Jamison, Kevin Brew, Kishore Natarajan, Gerald Gibson, Robert Bruce, Rinus Lee, Cory Wajda, Takaaki Tsunomura, Vijay Narayanan
62: (Invited) Interconnect Technology for the Angstrom Era and Beyond
International Workshop on Junction Technology, Kyoto, Japan, June 4 - 6, 2025
Rinus T.P. Lee, K. Imakita, G. Pattanaik, R. Yonezawa, K.H. Yu, J. Mayersky, H. Suzuki, C. Wajda
61: Development of High Thermal Conductance Wafer Bonding Interface With PVD Aluminum Nitride
IEEE 75th Electronic Components and Technology Conference (ECTC), Dallas, Texas, USA, May 27 - 30, 2025
Andrew Tuchman, Ayuta Suzuki, Christopher Netzband, Joshua Greklek, Rinus Lee, Ilseok Son
60: Process Control for the Modification of Ruthenium Resistivity in Scaled Subtractive Interconnects
IEEE International Conference on Interconnect Technology, San Jose, California USA, June 3 – 6, 2024
Jack Rogers, Hirokazu Aizawa, Nicholas Joy, Rinus Lee, Kenichi Imakita, Hojin Kim, Toru Hisamatsu
59: Thickness-Dependent Optical Properties of Metallic Thin Films and Their Correlation with Thermal Conductivity
Materials Research Society (MRS) Spring Meeting, Seattle, Washington, USA, April 23, 2024
Saman Zare, Md. Rafiqul Islam, Sean King, Christopher Jezewski, Colin Landon, Rinus Lee, Kanda Tapily, Colin Carver, Patrick Hopkins
58: A Study of Resistivity Control for Subtractive Interconnects Using Ruthenium
IEEE International Conference on Interconnect Technology, Dresden, Germany, May 22 – 25, 2023
Jack Rogers, Hirokazu Aizawa, Nicholas Joy, Sophia Rogalskyj, Rinus Lee, Kenichi Imakita, Kai-Hung Yu
57: Measuring the Phonon Contributions to Total Thermal Conductivity of Ruthenium and Tungsten Thin Films using a Steady-State Thermoreflectance Technique
American Physical Society March Meeting, Las Vegas, Nevada, USA, March 5 – 10, 2023
Md Rafiqul Islam, S. W King, K. Tapily, D. H Hirt, J. Tomko, C. Jezewski, C.D. Landon, K. Aryana, C. Carver, P. Hopkins, E.R. Hoglund, Rinus T.P. Lee
56: (Invited) Materials and Process Technologies for Scaling BEOL Interconnects
239th Electrochemical Society Meeting, (Virtual), May 30 – June 3, 2021
Rinus T.P. Lee, K. H. Yu, G. Pattanaik, R. Bourque, C. S. Wajda, and G. J. Leusink
55: Yield and Failure Analysis of FinFET Source to Drain Leakage in 14nm Technology
International Symposium for Testing and Failure Analysis, November 2020 (Virtual)
F. Beaudoin, S. Kodali, R. Deshpande, W. Zhao, E. Banghart, Rinus Lee, T. Mahalingam, Nuh Yusek, Wang Tao, Lillian Li, Sushruth Goud Perumalla, Shweta Arora, Trejo Rust
54: Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETs
Symposium on VLSI Technology, Honolulu, HI, USA, June 2018
Rinus T.P. Lee, N. Petrov, J. Kassim, M. Gribelyuk, J. Yang, L. Cao, K.B. Yeap, T. Shen, A.N. Zainuddin, A. Chandrashekar, S. Ray, E. Ramanathan, A.S. Mahalingam,
R. Chaudhuri, J. Mody, D. Damjanovic, Z. Sun, R. Sporer, T.J. Tang, H. Liu, J. Liu, B. Krishnan
53: (Invited) Low Temperature Microwave Annealing for CMOS Scaling
China Semiconductor Technology International Conference (CSTIC), Shanghai, China, March 2018
Rinus T.P. Lee, J. Kassim, R. Krishnan, B. Kannan, J. Rowland, A. Madan, D. Ferrer, J. Yang, S. Byrappa, J. Mody, M. Gribelyuk, W. Zhao, E. Kaganer, B. Yatzor, L. Huang,
J.P. Liu, B. Krishnan
52: (Late News) A 7nm CMOS Technology Platform for Mobile and High Performance Compute Application
International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 2017
S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A.K.M. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan, M. Eller, Y. Fan, Q. Fang, A. Gassaria, R. Gauthier, S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han, M. Hasan, J. Higman, J. Holt, L. Hu, L. Huang, C. Huang, T. Hung, Y. Jin, J. Johnson, S. Johnson, V. Joshi, M. Joshi, P. Justison, S. Kalaga, T. Kim, W. Kim, R. Krishnan, B. Krishnan, Anil K., M. Kumar, J. Lee, R. Lee, J. Lemon, S.L. Liew, P. Lindo, M. Lingalugari, M. Lipinski, P. Liu, J. Liu, S. Lucarini, W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski, J. Mehta, C. Meng, S. Mitra, C. Montgomery, H. Nayfeh, T. Nigam, G. Northrop, K. Onishi, C. Ordonio, M. Ozbek, R. Pal, S. Parihar, O. Patterson, E. Ramanathan, I. Ramirez, R. Ranjan, J. Sarad, V. Sardesai, S. Saudari, C. Schiller, B. Senapati, C. Serrau, N. Shah, T. Shen, H. Sheng, J. Shepard, Y. Shi, M.C. Silvestre, D. Singh, Z. Song, J. Sporre, P. Srinivasan, Z. Sun, A. Sutton, R. Sweeney, K. Tabakman, M. Tan, X. Wang, E. Woodard, G. Xu, D. Xu, T. Xuan, Y. Yan, J. Yang, K.B. Yeap, M. Yu, A. Zainuddin, J. Zeng, K. Zhang, M. Zhao, Y. Zhong, R. Carter,C-H. Lin, S. Grunow, C. Child, M. Lagus, R. Fox, E. Kaste, G. Gomba, S. Samavedam, P. Agnello, and DK Sohn
51: (Invited) Benchmarking Source/Drain Doping and Contact Technology Options for III-V Semiconductor Devices
9th International Conference on Materials for Advanced Technologies, Singapore, June 2017
Rinus T.P. Lee
50: Effects of Metal Orientation and Alloying on Metal-Semiconductor Schottky Barriers
APS March Meeting, New Orleans, LA, March 2017
Eduardo C. Silva, Domingo A. Ferrer, Israel Ramirez , Praneet Adusumilli , Oscar D. Restrepo, Rinus Lee, Wonwoo Kim, Murali Kota
49: (Invited) Heterogeneous Integration of III-V Semiconductors on Silicon for Electronics
229th ECS Meeting, San Diego CA, USA, June 2016
Rinus T.P. Lee
48: 10nm Nominal Channel Length MoS2 FETs with EOT 2.5nm and 0.52mA/um Drain Current
Device Research Conference, Columbus OH, USA, June 2015
L. Yang, R.T.P. Lee, S.S. Papa Rao, W. Tsai and P.D. Ye
47: (Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs
227th ECS Meeting, Chicago IL, USA, May 24 – 28, 2015
Rinus T.P. Lee, W.Y. Loh, R. Tieckelmann, T. Orzali, C. Huffman, A. Vert, G. Huang, M. Kelman, Z. Karim, C. Hobbs, R.J.W Hill and S.S. Papa Rao
46: Arsenic Monolayer Doping for Si and Ge Semiconductors
Surface Preparation and Cleaning Conference (SPCC) Saratoga Springs, NY, USA, May 12 – 14, 2015
W.-Y. Loh, C.H. Chen, R. Tieckelmann, Rinus T.P. Lee, E. Bersch, B. Sapp, C. Hobbs, S. Papa Rao, T. Cameron, T. Baum, J.-F. Zheng, S. Dimascio, D. Elzer, A. Avila, J. O’Neil, K. Fuse, M. Sato, N. Fujiwara, L. Chang, H. Uchida
45: 300mm Wafer Level Sulfur Monolayer Doping for III-V Materials
Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs NY, USA, May 3 – 6, 2015
W.Y. Loh, R.T.P. Lee, R. Tieckelmann, T. Orzali, B. Sapp, C. Hobbs, S.S. Papa Rao, K. Fuse, M. Sato, N. Fujiwara, L. Chang and H. Uchida
44: Ultra Low Contact Resistivity (<1×10-8 Ω-cm2) to In0.53Ga0.47As Fin Sidewalls (110)/(100) Surfaces: Realized with a VLSI Processed III-V Fin TLM Structure fabricated with III-V on Si Substrates
International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 15 – 17, 2014
Rinus T.P. Lee, Y. Ohsawa, C. Huffman, Y. Trickett, G. Nakamura, C. Hatem, K.V. Rao, F. Khaja, R. Lin, K. Matthews, A Jensen, T. Karpowicz, Peter F. Nielsen, E. Stinzianni,
A. Cordes, P.Y. Hung, D.-H. Kim, R.J.W. Hill, W.Y. Loh, C. Hobbs
43: VLSI processed InGaAs on Si MOSFETs with Thermally Stable, Self-Aligned Ni-InGaAs Contacts Achieving: Enhanced Drive Current and Pathway Towards a Unified Contact Module
International Electron Device Meeting (IEDM), Washington, DC, USA, December 9 – 11, 2013
Rinus T.P. Lee, R.J.W Hill, W-Y Loh, R-H Baek, S. Deora, K. Matthews, C. Huffman, K. Majumdar, T. Michalak, C. Borst, P.Y. Hung, C-H Chen, J-H Yum, T-W Kim, C.Y. Kang, W-E Wang, D-H Kim, C. Hobbs, P.D. Kirsch
42: High Voltage GaN Technology in a Silicon CMOS Environment: Challenges and Opportunities
224th ECS Meeting, San Francisco, CA, Oct 2 – Nov 1, 2013
Rusty Harris, Derek W Johnson, Richard J.W. Hill, Ed Piner, Man Hoi Wong, Rinus T.P. Lee
41: Relays do not leak – CMOS does
50th Design Automation Conference (DAC), Austin, TX, USA, May 29 – June 7, 2013
H. Fariborzi, Fred Chen, R. Nathanael, I-R. Chen, L. Hutin, R. Lee, T.-J. K. Liu
40: ETB-QW InAs MOSFET with Scaled Body for Improved Electrostatics
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 13, 2012
T-W Kim, D-H Kim, D-H Koh, RJW Hill, Rinus T.P. Lee, Man Hoi Wong, T. Cunningham, Jesús A Del Alamo, Sanjay Kumar Banerjee, S. Oktyabrsky, A. Greene, Y. Ohsawa, Y. Trickett, G. Nakamura, Qiang Li, Kei May Lau, C. Hobbs, Paul D Kirsch, Raj Jammy
39: (Invited) Emerging CMOS and Beyond CMOS Technologies for an Ultra-Low Power 3D World
IEEE International Conference on IC Design & Technology (ICICDT), Austin, TX, USA, May 30 – Jun 1, 2012
C.Y. Kang, K.W. Ang, R. Hill, W.Y. Loh, J Oh, R. Lee, David Gilmer, Gennadi Bersuker, C. Hobbs, Paul Kirsch, Klaus Hummler, S. Arkalgud, Raj Jammy
38: (Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic
221st ECS Meeting. Seattle, Washington, May 6-10, 2012
R. J. W. Hill, W.Y. Loh, J. Huang, T. Kim, R. Lee, W.E. Wang, J. Oh, C. Hobbs, P. D. Kirsch, R. Jammy
37: Scaled Micro-Relay Structure with Low Strain Gradient for Reduced Operating Voltage
221st ECS Meeting. Seattle, Washington, May 6-10, 2012
I-Ru Chen, Louis Hutin, Chanro Park, Rinus Lee, Rhesa Nathanael, Jack Yaung, Jaeseok Jeon, Tsu-Jae King Liu
36: (Invited) Challenges of III–V materials in Advanced CMOS logic
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 23 – 25, 2012
P.D. Kirsch, R.J.W Hill, J Huang, W.Y. Loh, T-W Kim, M.H. Wong, B.G. Min, C. Huffman, D. Veksler, C.D. Young, K.W. Ang, I. Ali, R.T.P. Lee, T. Ngai, A. Wang, W-E Wang,
T.H. Cunningham, Y.T. Chen, P.Y. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J.C. Lee, G. Bersuker, C. Hobbs, R. Jammy
35: Silicon-Carbon S/D Stressors: Integration of a Novel Nickel Aluminide-Silicide and Post-SPE Anneal for Reduced Schottky-Barrier and Leakage
216th ECS Meeting, Vienna, Austria, October 4 – 9, 2009
S.M. Koh, Wei-Jing Zhou, Rinus T.P. Lee, Mantavya Sinha, Chee-Mang Ng, Zhiyong Zhao, Helen Maynard, Naushad Variam, Yuri Erokhin, Ganesh Samudra, Yee-Chia Yeo
34: (Invited) Advanced Contact Technology for MOSFETs: Integration of New Materials for Series Resistance Reduction
216th ECS Meeting, Vienna, Austria, October 4 – 9, 2009
Yee-Chia Yeo, Rinus T.P. Lee
33: Single Silicide Comprising Nickel-Dysprosium Alloy for Integration in p-and n-FinFETs with Independent Control of Contact Resistance by Aluminum Implant
Symposium on VLSI Technology, Honolulu, HI, USA, June 16-18, 2009
Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo
32: Sulfur Segregation at the Platinum Silicide: Silicon:Carbon Interface for Electron Barrier Height Reduction: An Approach to Enable Independent Control of Contact Resistances for n- and p-channel FinFETs with a Single Metal Silicide
European MRS Spring Meeting, Strasbourg, France, June 8 – 12, 2009
R.T.P. Lee, D.Z. Chi, and Y.C. Yeo
31: Integration of Al segregated NiSiGe/SiGe Source/Drain Contact Technology in p-FinFETs for Drive Current Enhancement
215th ECS Meeting, San Francisco, CA, May 24 – 29, 2009
Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo
30: p-FinFETs with Al Segregated NiSi/p+-Si Source/Drain Contact Junction for Series Resistance Reduction
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 27 – 29, 2009
Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo
29: Schottky-Barrier Height Tuning of Nickel Silicide on Epitaxial Silicon-Carbon Films with High Substitutional Carbon Content
International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 23-26, 2008
P. S. Y. Lim, R. T. P. Lee, A. E. J. Lim, A. T. Y. Koh, M. Sinha, D. Z. Chi, Y. C. Yeo
28: 5nm Gate Length NW-FETs and Planar UTB-FETs with Pure Ge S/D Stressors and Laser-Free Melt-Enhanced Dopant Diffusion and Activation Technique
Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008
Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Ben L-H Tan, Ganesh S. Samudra, N Balasubramanian, Yee-Chia Yeo
27: Novel and Cost-Efficient Single Metallic Silicide Integration Solution with Dual Schottky-Barrier Achieved by Aluminum Inter-Diffusion for FinFET CMOS Technology with Enhanced Performance
Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008
Rinus T.P. Lee, Alvin T.Y. Koh, W. W. Fang, K.M. Tan, Andy E.J. Lim, T.Y. Liow, S.Y. Chow, A. M Yong, H.S. Wong, G.Q. Lo, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo
26: Selenium Co-implantation and Segregation as a New Contact Technology for Nanoscale SOI N-FETs featuring NiSi:C formed on Si:C S/D S Stressors
Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008
H.S. Wong, F.Y. Liu, K.W. Ang, S.M. Koh, Alvin T.Y. Koh, T.Y. Liow, Rinus T. P. Lee, Andy E.J. Lim, W.W. Fang, M. Zhu, L. Chan, N Balasubramaniam, G. Samudra, Yee-Chia Yeo
25: Strained FinFETs with In-situ Doped Si 1-y C y S/D Stressors: Performance Boost with Lateral Stressor Encroachment and High Substitutional Carbon Content
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 21 – 23, 2008
T.Y. Liow, K.M. Tan, Doran Weeks, Rinus T.P. Lee, Ming Zhu, K.M. Hoe, C.H. Tung, M Bauer, J. Spear, S. G Thomas, Ganesh S. Samudra, N Balasubramanian, Yee-Chia Yeo
24: A New Salicidation Process with Solid Antimony Segregation for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors
VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 21 – 23, 2008
Hoong-Shing Wong, Alvin Tian-Yi Koh, Hock-Chun Chin, Rinus Tek-Po Lee, Lap Chan, Ganesh Samudra, Yee-Chia Yeo
23: Photoemission Study of Energy Band Alignment of Ge2Sb2Te5 and Common CMOS Materials
MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008
Lina Wei-Wei Fang, Ji-Sheng Pan, Andy Eu-Jin Lim, Rinus Tek-Po Lee, Minghua Li, Rong Zhao, Luping Shi, Tow-Chong Chong, Yee-Chia Yeo
22: Formation of Nickel-Based Germanosilicide Contacts on Silicon-Germanium-Tin (Si1-x-yGexSny) Source/Drain Stressors
MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008
R.T.P. Lee, F.Y. Liu, K.M. Tan, A.E.-J. Lim, T.Y. Liow, S. Tripathy, G.S. Samudra, D.Z. Chi, and Y.C. Yeo
21: Contact Technology for Germanium-Tin (GeSn) Source/Drain using Nickel and Nickel-Platinum Alloys
MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008
G.H. Wang, E.-H. Toh, R.T.P. Lee, X.-C. Wang, D.H.L. Seng, S. Tripathy, Y.- L. Foo, G. Samudra, and Y.-C. Yeo
20: Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs
MRS Spring Meeting, San Francisco, CA, USA, April 9 – 13, 2007
Rinus Tek Po Lee, Kian-Ming Tan, Tsung-Yang Liow, Andy Eu-Jin Lim, Guo-Qiang Lo, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo
19: Interface Dipole Mechanism and NMOS Ni-FUSI Gate Work Function Engineering using Rare-Earth Metal (RE)-Based Dielectric Interlayers
International Semiconductor Device Research Symposium (ISDRS), Maryland, MD, Dec 12 – 14, 2007
Andy Eu-Jin Lim, Wei-Wei Fang, Fangyue Liu, Rinus T.P. Lee, Ganesh S Samudra, Dim-Lee Kwong, Yee-Chia Yeo
18: A New Liner Stressor with Very High Intrinsic Stress (≫ 6 GPa) and Low Permittivity Comprising Diamond-Like Carbon for Strained P-Channel Transistors
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 12, 2007
K.M. Tan, Ming Zhu, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Keat Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo
17: Route to Low Parasitic Resistance in MuGFETs with Silicon-Carbon S/D: Integration of Novel Low Barrier Ni(M)Si:C Metal Silicides and Pulsed Laser Annealing
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 12, 2007
Rinus Tek-Po Lee, Alvin Tian-Yi Koh, Fang-Yue Liu, Wei-Wei Fang, Tsung-Yang Liow, Kian-Ming Tan, Poh-Chong Lim, Andy Eu-Jin Lim, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, Guo-Qiang Lo, Xincai Wang, David Kuang-Yong Low, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo
16: Strained N-channel FinFETs with High-Stress Nickel Silicide-Carbon Contacts and Integration with FUSI Metal Gate Technology
International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 18 – 21, 2007
Tsung-Yang Liow, R.T.P Lee, K.M. Tan, M. Zhu, K.M. Hoe, G.S. Samudra, N Balasubramanian, Y.C. Yeo
15: Contact Technology Employing Nickel-Platinum Germanosilicide Alloys for p-Channel FinFETs with Silicon-Germanium Source and Drain Stressors
International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 18 – 21, 2007
R.T.P. Lee, K.M. Tan, A. E.-J. Lim, T.Y. Liow, X.C. Chen, M. Zhu, A.T.Y. Koh, K.M. Hoe, S.Y. Chow, G.Q. Lo, G.S. Samudra, D.Z. Chi, Y.C. Yeo
14: Strain Enhancement in Spacer-Less N-channel FinFETs with Silicon-Carbon Source and Drain Stressors
37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 11 – 13, 2007
Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Keat-Mun Hoe, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo
13: Band edge NMOS Work Function for Nickel Fully-Silicided (FUSI) Gate obtained by the Insertion of Novel Y-, Tb-, and Yb-based Interlayers
37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 11 – 13, 2007
Andy Eu-Jin Lim, Rinus TP Lee, Xin Peng Wang, Wan Sik Hwang, Chih-Hang Tung, Doreen MY Lai, Ganesh Samudra, Dim-Lee Kwong, Yee-Chia Yeo
12: Novel Epitaxial Nickel Aluminide-Silicide with Low Schottky-Barrier and Series Resistance for Enhanced Performance of Dopant-Segregated S/D N-MuGFETs
Symposium on VLSI Technology, Kyoto, Japan, June 12 – 16, 2007
Rinus TP Lee, T.Y. Liow, K.M. Tan, Andy E.J. Lim, Chee-Seng Ho, Keat-Mum Hoe, M.Y. Lai, Thomas Osipowicz, Guo-Qiang Lo, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo
11: Material and Electrical Characterization of Nickel Silicide-Carbon as Contact Metal to Silicon-Carbon Source and Drain Stressors
MRS Spring Meeting, San Francisco, CA, USA, April 9 – 13, 2007
Rinus Tek Po Lee, Li-Tao Yang, Kah-Wee Ang, Tsung-Yang Liow, Kian-Ming Tan, Andrew See-Weng Wong, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo
10: Carrier Transport Characteristics of sub-30 nm Strained n-Channel FinFETs Featuring Si:C S/D Regions and Methods for Further Performance Enhancement
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 11 – 13, 2006
Tsung-Yang Liow, Kian-Ming Tan, Hock-Chun Chin, Rinus T.P. Lee, Chih-Hang Tung, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo
09: Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in n-Channel Multiple-Gate Transistors with Sub-35nm Gate Length
International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 11 – 13, 2006
Rinus T.P. Lee, T.Y. Liow, K.M. Tan, Andy E.J. Lim, H.S. Wong, P.C. Lim, Doreen MY Lai, Guo-Qiang Lo, Chih-Hang Tung, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo
08: Sub-30 nm Strained p-Channel FinFETs with Condensed SiGe Source/Drain Stressors
International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 12 – 15, 2006
K.M. Tan, T.Y. Liow, R.T.P. Lee, K.J. Chui, C.H. Tung, N. Balasubramanian, G.S. Samudra, W.J. Yoo, Y.C. Yeo
07: Sub-30 nm P-channel Schottky Source/Drain FinFETs: Integration of Pt3Si FUSI Metal Gate and High-K Dielectric
International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 12 – 15, 2006
R.T.P. Lee, K.M. Tan, A.E-J Lim, T.Y. Liow, G.Q. Lo, G. Samudra, D.Z. Chi, Y.C. Yeo
06: Strained n-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement
Symposium on VLSI Technology, Honolulu, HI, USA, June 13 – 17, 2006
T-Y Liow, K-M Tan, R. Lee, Anyan Du, C-H Tung, G Samudra, W-J Yoo, N Balasubramanian, Y-C Yeo
05: Material and Electrical Characterization of Ni-and Pt-Germanides for p-Channel Germanium Schottky Source/Drain Transistors
International Workshop on Junction Technology (IWJT), Shanghai, China, May 15 – 16, 2006
H.B. Yao, C.C. Tan, S.L. Liew, C.T. Chua, C.K. Chua, R. Li, R.T.P. Lee, S.J. Lee, D.Z. Chi
04: Process-Induced Strained p-MOSFET Featuring Nickel-Platinum Silicided Source/Drain
MRS Spring Meeting, San Francisco, CA, USA, April 17 – 21, 2006
Rinus Tek Po Lee, Tsung-Yang Liow, Kian-Ming Tan, Kah-Wee Ang, King-Jien Chui, Qiang-Lo Guo, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia YeO
03: Material and Electrical Characterization of Nickel Germanide for p-Channel Germanium Schottky Source/Drain Transistors
International Conference on Solid State Devices and Materials (SSDM), Kobe, Japan, September 12 – 15, 2005
R.T.P. Lee, S.L. Liew, B Balakrishnan, K.Y. Lee, Y.C. Yeo, D.Z. Chi
02: (Invited) Addressing Materials and Process-Integration Issues of NiSi Silicide Process using Impurity Engineering
International Workshop on Junction Technology (IWJT), Shanghai, China, March 16, 2004
D.Z. Chi, R.T.P. Lee, S.J. Chua
01: NiSi formation in the Ni (Ti)/SiO2/Si System
MRS Spring Meeting, San Francisco, CA, USA, March 12 – 16, 2004
R.T.P. Lee, D.Z. Chi, S.J. Chua
JOURNAL PUBLICATIONS
50: Unveiling Phonon Contributions to Thermal Conductivity and the Applicability of the Wiedemann—Franz Law in Ruthenium and Tungsten Thin Films
Advanced Functional Materials, e11592, 2025
Md. Rafiqul Islam, P. Karna, N. Bhatt, S. Thakur, H. Heinrich, D.M. Hirt, S. Zare, C. Jezewski, R.T.P. Lee, K. Tapily, J. T. Gaskins, C. D. Landon, S. W. King, A. Giri, P.E. Hopkins
49: (Invited) Scaling Challenges for Advanced CMOS Devices
International Journal of High Speed Electronics and Systems 26, p.1740001, 2017
A.P. Jacob, R. Xie, M.G. Sung, L. Liebmann, Rinus T.P. Lee, B. Taylor
48: Investigation of the Thermal Stability of Mo-In0. 45Ga0. 47As for Applications as Source/Drain Contacts
Journal of Applied Physics 120 (13), p.135303, 2016
Lee A. Walsh, Conan Weiland, Anthony P. McCoy, Joseph C. Woicik, Rinus T.P. Lee, Pat Lysaght, Greg Hughes
47: Heavily Tellurium Doped n-Type InGaAs Grown by MOCVD on 300mm Si wafers
Journal of Crystal Growth 426, pp. 243-247, 2015
Tommaso Orzali, Alexey Vert, Rinus T.P. Lee, Aras Norvilas, Gensheng Huang, Joshua L Herman, Richard J.W. Hill, Satyavolu S. Papa Rao
46: Ni-(In, Ga) As Alloy Formation Investigated by Hard-X-ray Photoelectron Spectroscopy and X-ray Absorption Spectroscopy
Physical Review Applied 2 (6), p. 064010, 2014
Lee A Walsh, Greg Hughes, Conan Weiland, Joseph C Woicik, Rinus TP Lee, Wei-Yip Loh, Pat Lysaght, Chris Hobbs
45: Very Low Resistance Alloyed Ni-Based Ohmic Contacts to InP-Capped and Uncapped n+ In0. 53Ga0. 47As
Journal of Applied Physics 116 (16), p. 164506, 2014
M. Abraham, S.Y. Yu, W.H. Choi, R.T.P. Lee, S.E. Mohney
44: Challenges of Contact Module Integration for GaN-Based Devices in a Si-CMOS Environment
Journal of Vacuum Science & Technology B 32 (3) p.030606, 2014
Derek W. Johnson, Pradhyumna Ravikirthi, Jae Woo Suh, Rinus T.P. Lee, Richard J.W. Hill, Man Hoi Wong, Edwin L. Piner, Harlan Rusty Harris
43: (Invited) Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs
IEEE Transactions on Device and Materials Reliability 13 (4), pp. 507-514, 2013
S. Deora, G. Bersuker, W-Y Loh, D. Veksler, K. Matthews, T.W. Kim, R.T.P. Lee, R.J.W. Hill, D-H Kim, W-E Wang, C Hobbs, P.D. Kirsch
42: Threshold Voltage Shift due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology
IEEE Transactions on Electron Devices 60 (10), pp. 3197-3203, 2013
Derek W. Johnson, Rinus T.P. Lee, Richard J.W. Hill, Man Hoi Wong, Gennadi Bersuker, Edwin L. Piner, Paul D. Kirsch, H. Rusty Harris
41: Contact Resistance Reduction Technology using Aluminum Implant and Segregation for Strained p-FinFETs with Silicon–Germanium Source/Drain
IEEE Transactions on Electron Devices 57 (6), pp. 1279-1286, 2010
M. Sinha, R.T.P Lee, E.F. Chor, Y.C. Yeo
40: Schottky Barrier Height Modulation of Nickel–Dysprosium-Alloy Germanosilicide Contacts for Strained P-FinFETs
IEEE Electron Device Letters 30 (12), pp. 1278-1280, 2009
M. Sinha, R.T.P. Lee, E.F. Chor, Y.C. Yeo
39: The Role of Carbon and Dysprosium in Ni[Dy]Si:C Contacts for SBH Reduction and Application in N-Channel MOSFETs With Si:C S/D Stressors
IEEE Transactions on Electron Devices 56 (11), pp. 2770-2777, 2009
R.T.P. Lee, A.T.Y. Koh, K.M. Tan, T.Y. Liow, D.Z. Chi, Y.C. Yeo
38: Silicon: Carbon S/D Stressors: Integration of a Novel Nickel Aluminide-Silicide and Post-Solid-Phase-Epitaxy Anneal for reduced Schottky-Barrier and Leakage
ECS Transactions 25 (7), pp. 211-216, 2009
Shao Ming Koh, Wei-Jing Zhou, Rinus T.P. Lee, Mantavya Sinha, Chee-Mang Ng, Zhiyong Zhao, Helen Maynard, Naushad Variam, Yuri Erokhin, Ganesh Samudra, Yee-Chia Yeo
37: Effect of Substitutional Carbon Concentration on Schottky-Barrier Height of Nickel Silicide formed on Epitaxial Silicon-Carbon Films
Journal of Applied Physics 106 (4), p. 043703, 2009
P.S.Y. Lim, R.T.P. Lee, M. Sinha, D.Z. Chi, Y.C. Yeo
36: Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors (FinFETs)
IEEE Transactions on Electron Devices 56 (7), pp. 1458-1465, 2009
R.T.P. Lee, D.Z. Chi, Y.C. Yeo
35: Ultra High-Stress Liner comprising Diamond-Like Carbon for Performance Enhancement of p-Channel Multiple-Gate Transistors
IEEE Transactions on Electron Devices 56 (6), pp. 1277-1283, 2009
K.M. Tan, M. Yang, T.Y. Liow, R.T.P. Lee, Y.C. Yeo
34: Integration of Al Segregated NiSiGe/SiGe Source/Drain Contact Technology in p-FinFETs for Drive Current Enhancement
ECS Transactions 19 (1), pp. 323-330, 2009
M Sinha, RTP Lee, SN Devi, GQ Lo, EF Chor, YC Yeo
33: Sulfur-Induced PtSi: C/Si: C Schottky Barrier Height lowering for Realizing n-channel FinFETs with Reduced External Resistance
IEEE Electron Device Letters 30 (5), pp. 472-474, 2009
R.T.P. Lee, A.E.J. Lim, K.M. Tan, T.Y. Liow, D.Z. Chi, Y.C. Yeo
32: Achieving Sub-0.1 eV Hole Schottky Barrier Height for NiSiGe on SiGe by Aluminum Segregation
Journal of The Electrochemical Society 156 (4), pp. H233-H238, 2009
M. Sinha, R.T.P. Lee, A. Lohani, S. Mhaisalkar, E.F. Chor, Y.C. Yeo
31: Performance Benefits of Diamond-Like Carbon Liner Stressor in Strained p-channel Field-Effect Transistors with Silicon–Germanium Source and Drain
IEEE Electron Device Letters 30 (3), pp. 250-253, 2009
K.M. Tan, M. Yang, W.W. Fang, A.E.J. Lim, R.T.P. Lee, T.Y. Liow, Y.C. Yeo
30: Novel Aluminum Segregation at NiSi/p+-Si Source/Drain Contact for Drive Current Enhancement in P-Channel FinFETs
IEEE Electron Device Letters 30 (1), pp. 85-87, 2009
M. Sinha, R.T.P. Lee, K.M. Tan, G.Q. Lo, E.F. Chor, Y.C. Yeo
29: Strained Silicon Nanowire Transistors with Germanium Source and Drain Stressors
IEEE Transactions on Electron Devices 55 (11), pp. 3048-3055, 2008
Tsung-Yang Liow, Kian-Ming Tan, Rinus Tek Po Lee, Ming Zhu, Ben Lian-Huat Tan, N Balasubramanian, Yee-Chia Yeo
28: Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon (Si1−yCy) Source and Drain Stressors With High Carbon Content
IEEE Transactions on Electron Devices 55 (9), pp. 2475-2483, 2008
Tsung-Yang Liow, K.M. Tan, D. Weeks, R.T.P. Lee, M. Zhu, K.M. Hoe, C.H. Tung, M. Bauer, J. Spear, S.G. Thomas, G.S. Samudra, N Balasubramanian, Yee-Chia Yeo
27: Novel Rare-Earth Dielectric Interlayers for Wide NMOS Work-Function Tunability in Ni-FUSI Gates
IEEE Transactions on Electron Devices 55 (9), pp. 2370-2377, 2008
A.E.J. Lim, R.T.P. Lee, G.S. Samudra, D.L. Kwong, Y.C. Yeo
26: Modification of Molybdenum Gate Electrode Work Function via (La-, Al-Induced) Dipole Effect at High-k/SiO2 Interface
IEEE Electron Device Letters 29 (8), pp. 848-851, 2008
Andy Eu-Jin Lim, Rinus Tek Po Lee, Ganesh S Samudra, Dim-Lee Kwong, Yee-Chia Yeo
25: Diamond-Like Carbon (DLC) liner: A New Stressor for p-channel Multiple-Gate Field-Effect Transistors
IEEE Electron Device Letters 29 (7), pp. 750-752, 2008
Kian-Ming Tan, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Narayanan Balasubramanian, Yee-Chia Yeo
24: Germanium Source and Drain stressors for Ultrathin-Body and Nanowire Field-Effect Transistors
IEEE Electron Device Letters 29 (7), pp. 808-810, 2008
Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Ben L-H Tan, N Balasubramanian, Yee-Chia Yeo
23: Pulsed Laser Annealing of Silicon-Carbon Source/Drain in MuGFETs for Enhanced Dopant Activation and High Substitutional Carbon Concentration
IEEE Electron Device Letters 29 (5), pp. 464-467, 2008
Alvin Tian-Yi Koh, Rinus Tek-Po Lee, Fang-Yue Liu, Tsung-Yang Liow, Kian Ming Tan, Xincai Wang, Ganesh S Samudra, N Balasubramanian, Dong-Zhi Chi, Yee-Chia Yeo
22: P-Channel Tri-Gate FinFETs Featuring Ni1−yPty SiGe Source/Drain Contacts for Enhanced Drive Current Performance
IEEE Electron Device Letters 29 (5), pp. 438-441, 2008
R.T.P. Lee, K.M. Tan, A.E.J. Lim, T.Y. Liow, G.S. Samudra, D.Z. Chi, Y.C. Yeo
21: Effectiveness of Aluminum Incorporation in Nickel Silicide and Nickel Germanide Metal Gates for Work Function Reduction
Japanese Journal of Applied Physics 47 (4S), p. 2383, 2008
A.E.J. Lim, R.T.P. Lee, A.T.Y. Koh, G.S. Samudra, D.L. Kwong, Y.C. Yeo
20: Novel Extended-Pi Shaped Silicon–Germanium S/D Stressors for Strain and Performance Enhancement in p-Channel Tri-Gate Fin-Type Field-Effect Transistor
Japanese Journal of Applied Physics 47 (4S), p.2589, 2008
Kian-Ming Tan, Tsung-Yang Liow, Rinus T.P. Lee, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo
19: Achieving Conduction Band-Edge SBH for Arsenic-Segregated Nickel Aluminide Disilicide and Implementation in FinFETs with Ultra-Narrow Fin Widths
IEEE Electron Device Letters 29 (4), pp. 382-385, 2008
Rinus Tek-Po Lee, Tsung-Yang Liow, Kian-Ming Tan, Andy Eu-Jin Lim, Alvin Tian-Yi Koh, Ming Zhu, Guo-Qiang Lo, Ganesh S. Samudra, Dong Zhi Chi, Yee-Chia Yeo
18: Nickel-Aluminum Alloy Silicides with High Aluminum Content for Contact Resistance Reduction and Integration in n-channel Field-Effect Transistors
Journal of The Electrochemical Society 155 (3), pp. H151-H155, 2008
Alvin Tian-Yi Koh, Rinus Tek-Po Lee, Andy Eu-Jin Lim, Doreen Mei-Ying Lai, Dong-Zhi Chi, Keat-Mun Hoe, N. Balasubramanian, Ganesh S. Samudra, Yee-Chia Yeo
17: A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-channel MOSFET
IEEE Electron Device Letters 29 (2), 192-194, 2008
Kian-Ming Tan, Ming Zhu, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Keat Mun Hoe, C.H. Tung, N. Balasubramanian, G.S. Samudra, Yee-Chia Yeo
16: Spacer Removal Technique for Boosting Strain in n-channel FinFETs with Silicon-Carbon Source and Drain Stressors
IEEE Electron Device Letters 29 (1), pp. 80-82, 2008
Tsung-Yang Liow, Kian-Ming Tan, Rinus TP Lee, Ming Zhu, Keat-Mun Hoe, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo
15: Nickel-Silicide:Carbon Contact Technology for n-channel MOSFETs with Silicon–Carbon Source/Drain
IEEE Electron Device Letters 29 (1), pp. 89-92, 2008
Rinus TP Lee, L.T. Yang, T.Y. Liow, K.M. Tan, Andy E.J. Lim, K.W. Ang, Doreen M.Y. Lai, K.M. Hoe, G.Q. Lo, G.S. Samudra, Dong Zhi Chi, Yee-Chia Yeo
14: N-Channel (110)-Sidewall Strained FinFETs with Silicon–Carbon Source and Drain Stressors and Tensile Capping Layer
IEEE Electron Device Letters 28 (11), 1014-1017, 2007
Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Chih-Hang Tung, Ganesh S. Samudra, N. Balasubramanian, Yee-Chia Yeo
13: Impact of Interfacial Dipole on Effective Work Function of Nickel Fully Silicided Gate Electrodes Formed on Rare-Earth-Based Dielectric Interlayers
Applied Physics Letters 91 (17), p172115, 2007
A.E.J. Lim, W.W. Fang, F. Liu, R.T.P. Lee, G. Samudra, D.L. Kwong, Y.C. Yeo
12: Strained p-Channel FinFETs With Extended Π Shaped Silicon–Germanium Source and Drain Stressors
IEEE Electron Device Letters 28 (10), 905-908, 2007
Kian-Ming Tan, Tsung-Yang Liow, Rinus TP Lee, Keat Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo
11: Addressing Materials and Integration Issues for NiSi Silicide Contact Metallization in Nano-Scale CMOS Devices
Thin Solid Films 515 (22), 8102-8108, 2007
D.Z. Chi, R.T.P. Lee, A.S.W. Wong
10: Probing the ErSi1. 7 Phase Formation by Micro-Raman Spectroscopy
Journal of The Electrochemical Society 154 (5), pp. H361-H364, 2007
Rinus Tek-Po Lee, Kian-Ming Tan, Tsung-Yang Liow, Chee-Sheng Ho, S Tripathy, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo
09: N-channel FinFETs with 25-nm Gate Length and Schottky-Barrier Source and Drain featuring Ytterbium Silicide
IEEE Electron Device Letters 28 (2), pp. 164-167, 2007
Rinus TP Lee, Andy Eu-Jin Lim, Kian-Ming Tan, Tsung-Yang Liow, Guo-Qiang Lo, Ganesh S Samudra, Dong Zhi Chi, Yee-Chia Yeo
08: Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET
IEEE Electron Device Letters 28 (6), pp. 482-485, 2007
A.E.J. Lim, R.T.P. Lee, X.P. Wang, W.S. Hwang, C.H. Tung, G.S. Samudra, D.L. Kwong, Y.C. Yeo
07: Drive-Current Enhancement in FinFETs using Gate-Induced Stress
IEEE Electron Device Letters 27 (9), pp. 769-771, 2006
K.M. Tan, T.Y. Liow, R.T.P. Lee, C.H. Tung, G.S. Samudra, W.J. Yoo, Y.C. Yeo
06: Enhanced Morphological Stability of NiGe films Formed using Ni(Zr) Alloy
Thin Solid Films 504 (1), pp. 104-107, 2006
S.L. Liew, R.T.P. Lee, K.Y. Lee, B. Balakrisnan, S.Y. Chow, M.Y. Lai, D.Z. Chi
05: Full Silicidation of Silicon Gate Electrodes Using Nickel-Terbium Alloy for MOSFET Applications
Journal of the Electrochemical Society 153 (4), p.G337, 2006
A.E.J. Lim, R.T.P. Lee, C.H. Tung, S. Tripathy, D.L. Kwong, Y.C. Yeo
04: Fully Silicided Ni1− x Pt x Si Metal Gate Electrode for p-MOSFETs
Electrochemical and Solid-State Letters 8 (7), pp. G156-G159, 2005
R.T.P. Lee, S.L. Liew, W.D. Wang, E.K.C. Chua, S.Y. Chow, M.Y. Lai, D.Z. Chi
03: Current–voltage Characteristics of Schottky Barriers with Barrier Heights Larger than the Semiconductor Band Gap: The Case of Ni Ge∕ n-(001) Ge Contact
Journal of Applied Physics 97 (11), p. 113706, 2005
D.Z. Chi, R.T.P. Lee, S.J. Chua, S.J. Lee, S. Ashok, D.L. Kwong
02: Effects of Ti incorporation in Ni on Silicidation Reaction and Structural/Electrical Properties of NiSi
Journal of The Electrochemical Society 151 (9), pp. G642-G647, 2004
R.T.P. Lee, D.Z. Chi, M.Y. Lai, N.L. Yakovlev, S.J. Chua
01: Maskless Process for Fabrication of Ultra-Fine Pitch Solder Bumps for Flip Chip Interconnects
J. Electronic Packaging 125 (4), pp. 597-601, 2003
R.T.P. Lee, D.Z. Chi, S.J. Chua
PATENTS
29: Single Diffusion Breaks Including Stacked Dielectric Layers
US11545574 B2, Jan 3, 2023, Haiting Wang, Rinus Lee, Sipeng Gu, Yue Hu
28. Asymmetric source/drain structures structures in a semiconductor device
US11362178 B2, June 14, 2022, Jeff Shu, Baofu Zhu, Rinus Tek Po Lee
27: Semiconductor Devices with Low Resistance Gate Structures
US11,145,716 B1, Oct 12, 2021, Lee Rinus Tek Po, Jiehui Shu
26: Multiple Threshold Voltage Devices
US11094598 B2, Aug 17, 2021, Bharat V Krishnan, Lee Rinus Tek Po, Jiehui Shu, Hyung Yoon Choi
25: Mask-Free Methods of Forming Structures in a Semiconductor Device
US11004953 B2, May 11, 2021, Lee Rinus Tek Po, Zang Hui, Jiehui Shu, Yu Hong, Hong Wei
24: Mask-Free Methods of Forming Structures in a Semiconductor Device
US10,896853 B2, Jan 19, 2021, Jiehui Shu, Lee Rinus Tek Po, Hong Wei, Zang Hui, Yu Hong
23: Devices with Highly Active Acceptor Doping and Method of Production Thereof
US10,886,178 B2, Jan 5, 2021, Lee Rinus Tek Po, Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan, Curtis Durfee
22: Spacer Structures for a Transistor Device
US10872979 B2, Dec 22, 2020, Hui Zang, Chung Foong Tang, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Lee Rinus Tek Po, Scott Beasor
21: Methods of Forming Spacers Adjacent to Gate Structures of a Transistor Device
US10629739 B2, Apr 21, 2020, Zang Hui, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Lee Rinus Tek Po, Scott Beasor
20: Memory Array with Buried Bitlines below Vertical Field Effect Transistors of Memory Cells and a Method of Forming the Memory Array
US10418365 B2, Sept 17, 2019, Zang Hui, Ciavatti Jerome, Lee Rinus Tek Po
19: Common Metal Contact Regions having Different Schottky Barrier Heights and Methods of Manufacturing Same
US10276683 B2, Apr 30, 2019, Rinus Tek Po Lee, Jinping Liu, Ruilong Xie
18: Methods, Apparatus, and Manufacturing System for Self-Aligned Patterning of Contacts in a Vertical Field Effect Transistor
US10263122 B1, Apr 16, 2019, Zang Hui, Xie Ruilong, Rinus Tek Po Lee, Lars Liebmann
17: Method for Forming a Protection Device having An Inner Contact Spacer and Resulting Devices
US10242982 B2, Mar 26, 2019, Xie Ruilong, Katsunori Onishi, Rinus Tek Po Lee
16: Vertical-Transport Transistors with Self-Aligned Contacts
US10230000 B2, Mar 12, 2019, Emilie Bourjot, Daniel Chanemougame, Rinus Tek Po Lee, Xie Ruilong, Hui Zang
15: Microwave Annealing of Flowable Oxides with Trap Layer
US10211045 B1, Feb 19, 2019, Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Rinus Tek Po Lee, Yiheng Xu
14: Methods, Apparatus and System for Vertical FinFET Device with Reduced Parasitic Capacitance
US10204904 B2, Feb 12, 2019, Zang Hui, Rinus Tek Po Lee
13: Integrated Circuit Products that Include FinFET Devices and a Protection Layer Formed on An Isolation Region
US10170544 B2, Jan 1, 2019, Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee
12: FinFETs with Strained Channels and Reduced on State Resistance
US10134876 B2, Nov 20, 2018 |PDF| Bharat Krishnan, Timothy McArdle, Rinus Tek Po Lee, Shishir Ray, Akshey Sehgal
11: Memory Array with Buried Bitlines Below Vertical Field Effect Transistors of Memory Cells and a Method of Forming the Memory Array
US10134739 B1, Nov 20, 2018, Zang Hui, Jerome Ciavatti, Rinus Tek Po Lee
10: Semiconductor Structure including Two-Dimensional and Three-Dimensional Bonding Materials
US10121706 B2, Nov 6, 2018, Rinus T.P. Lee, Bharat Krishnan, Zang Hui, Matthew Stoker
09: Buried Contact Structures for a Vertical Field-Effect Transistor
US10109714 B2 Oct 23, 2018, Zang Hui, Rinus Tek Po Lee
08: Nanosheet FET with Full Dielectric Isolation
US10103238 B1, Oct 16, 2018, Zang Hui, Rinus Tek Po Lee, Haigou Huang, Chanro Park, Ming Gyu Sung, Xie Ruilong
07: Methods of Forming a Protection Layer on An Isolation Region of IC products comprising FinFET Devices
US9876077 B1, Jan 23, 2018, Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee
06: Buried Contact Structures for a Vertical Field-Effect Transistor
US9831317 B1, Nov. 28, 2017, Hui Zang, Tek Po Rinus Lee
05: Common Metal Contact Regions having Different Schottky Barrier Heights and Methods of Manufacturing Same
US9812543 B2, Nov 07, 2017, Rinus Tek Po Lee, Jinping Liu, Ruilong Xie
04: Forming Symmetrical Stress Liners for Strained CMOS Vertical Nanowire Field-Effect Transistors
US9570552 B1, Feb, 14, 2017, Rinus Tek Po Lee, Jinping Liu
03: Metal Alloy with An Abrupt Interface to III-V Semiconductor
US8829567 B2, Sept 9, 2014, Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill
02: Silicide Formed from Ternary Metal Alloy Films
US7335606 B2, Feb 26, 2008, Dongzhi Chi, Tek Po Rinus, Soo Jin Chua
01: Forming an Electrical Contact on An Electronic Component
US7015132 B2, Mar 06, 2006, Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah
INTERNS (ALUMNI)
Name
Thomas Nelson
Evan Sweet
Yixin Qin
Daniel Teleshevsky
Mai Abdelmigeed
Gyana Biswal
Hwan Oh
Kieran Bohonan
Ritesh Chaudhuri
Ye Jia
Anna C. Smith
Sabrina Reid
Raphael Renner
Topic
EUV Patterning Films
Ferroelectric Films
High K Process
High K Characterization
Area Selective Deposition
Device Characterization
Area Selective Deposition
Advanced Interconnects
Device Resistance Scaling
Advanced Thermal Processing
Monolayer Doping for III-V FETs
Off-Grid Microsystems
Lifetime and Stability of OPV
School
Purdue University, USA
Rensselaer Polytechnic Institute, USA
University of Notre Dame, USA
Cornell University, USA
North Carolina State University, USA
University of Albany, NY, USA
North Carolina State University, USA
Rensselaer Polytechnic Institute, USA
City University of New York, USA
University of Buffalo, USA
Carnegie Mellon University, USA
Karlsruhe Institute of Technology, Germany
Max Planck Institute for Polymer Research, Germany
Year
2025
2025
2025
2025
2024
2024
2023
2022
2017
2016
2014
2011
2010