Conference Publications

  • 55: J. Kassim, R.T.P. Lee, R. Krishnan, J. Yang, D. Ferrer, Y. Shusterman, I. Ramirez, and B. Krishnan, “Low Temperature Microwave Anneal in FinFET Fabrication,” AIMES, Cancun, Mexico, Sept 30 – Oct 4, 2018

  • 54: Rinus T.P. Lee, N. Petrov, J. Kassim, M. Gribelyuk, J. Yang, L. Cao, K.B. Yeap, T. Shen, A.N. Zainuddin, A. Chandrashekar, S. Ray, E. Ramanathan, A.S. Mahalingam, R. Chaudhuri, J. Mody, D. Damjanovic, Z. Sun, R. Sporer, T.J. Tang, H. Liu, J. Liu, B. Krishnan, “Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETs,” Symposium on VLSI Technology, Honolulu, HI, USA,  June 18 – 22, 2018

  • 53: (Invited) Rinus T.P. Lee, J. Kassim, R. Krishnan, B. Kannan, J. Rowland, A. Madan, D. Ferrer, J. Yang, S. Byrappa, J. Mody, M. Gribelyuk, W. Zhao, E. Kaganer, B. Yatzor, L. Huang, J.P. Liu, B. Krishnan, “Low Temperature Microwave Annealing for CMOS Scaling,” China Semiconductor Technology International Conference (CSTIC), Shanghai, China, March 11 – 12, 2018

  • 52: (Late News) S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A.K.M. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan, M. Eller, Y. Fan, Q. Fang, A. Gassaria, R. Gauthier, S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han, M. Hasan, J. Higman, J. Holt, L. Hu, L. Huang, C. Huang, T. Hung, Y. Jin, J. Johnson, S. Johnson, V. Joshi, M. Joshi, P. Justison, S. Kalaga, T. Kim, W. Kim, R. Krishnan, B. Krishnan, Anil K., M. Kumar, J. Lee, R. Lee, J. Lemon, S.L. Liew, P. Lindo, M. Lingalugari, M. Lipinski, P. Liu, J. Liu, S. Lucarini, W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski, J. Mehta, C. Meng, S. Mitra, C. Montgomery, H. Nayfeh, T. Nigam, G. Northrop, K. Onishi, C. Ordonio, M. Ozbek, R. Pal, S. Parihar, O. Patterson, E. Ramanathan, I. Ramirez, R. Ranjan, J. Sarad, V. Sardesai, S. Saudari, C. Schiller, B. Senapati, C. Serrau, N. Shah, T. Shen, H. Sheng, J. Shepard, Y. Shi, M.C. Silvestre, D. Singh, Z. Song, J. Sporre, P. Srinivasan, Z. Sun, A. Sutton, R. Sweeney, K. Tabakman, M. Tan, X. Wang, E. Woodard, G. Xu, D. Xu, T. Xuan, Y. Yan, J. Yang, K.B. Yeap, M. Yu, A. Zainuddin, J. Zeng, K. Zhang, M. Zhao, Y. Zhong, R. Carter,C-H. Lin, S. Grunow, C. Child, M. Lagus, R. Fox, E. Kaste, G. Gomba, S. Samavedam, P. Agnello, and DK Sohn, A 7nm CMOS Technology Platform for Mobile and High Performance Compute Application,” International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 02 – 06, 2017

  • 51: (Invited) Rinus T.P. Lee, “Benchmarking Source/Drain Doping and Contact Technology Options for III-V Semiconductor Devices,” 9th International Conference on Materials for Advanced Technologies, Singapore, June 18 – 23, 2017

  • 50: Eduardo C. Silva , Domingo A. Ferrer , J. Israel Ramirez , Praneet Adusumilli , Oscar D. Restrepo , Rinus Lee , Wonwoo Kim , Murali Kota, “Effects of Metal Orientation and Alloying on Metal-Semiconductor Schottky Barriers,” APS March Meeting, New Orleans, LA, March 13 – 17, 2017

  • 49: (Invited) Rinus T.P. Lee, “Heterogeneous Integration of III-V Semiconductors on Silicon for Electronics,” 229th ECS Meeting, San Diego CA, USA, May 29 – June 2, 2016

  • 48: L. Yang, R.T.P. Lee, S.S. Papa Rao, W. Tsai and P.D. Ye, “10nm Nominal Channel Length MoS2 FETs with EOT 2.5nm and 0.52mA/um drain current,” Device Research Conference, Columbus OH, USA, June 21 – 24, 2015

  • 47: (Invited) Rinus T.P. Lee, W.Y. Loh, R. Tieckelmann, T. Orzali, C. Huffman, A. Vert, G. Huang, M. Kelman, Z. Karim, C. Hobbs, R.J.W Hill and S.S. Papa Rao, “Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs,” 227th ECS Meeting, Chicago IL, USA,  May 24 – 28, 2015

  • 46: W.-Y. Loh, C.H. Chen, R. Tieckelmann, Rinus T.P. Lee, E. Bersch, B. Sapp, C. Hobbs, S. Papa Rao, T. Cameron, T. Baum, J.-F. Zheng, S. Dimascio, D. Elzer, A. Avila, J. O’Neil, K. Fuse, M. Sato, N. Fujiwara, L. Chang, H. Uchida, “Arsenic Monolayer Doping for Si and Ge Semiconductors,” Surface Preparation and Cleaning Conference (SPCC), Saratoga Springs, NY, USA, May 12 – 14, 2015

  • 45: W.Y. Loh, R.T.P. Lee, R. Tieckelmann, T. Orzali, B. Sapp, C. Hobbs, S.S. Papa Rao, K. Fuse, M. Sato, N. Fujiwara, L. Chang and H. Uchida, “300mm Wafer Level Sulfur Monolayer Doping for III-V Materials,” Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs NY, USA, May 3 – 6, 2015

  • 44: Rinus T.P. Lee, Y. Ohsawa, C. Huffman, Y. Trickett, G. Nakamura, C. Hatem, K.V. Rao, F. Khaja, R. Lin, K. Matthews, A Jensen, T. Karpowicz, Peter F. Nielsen, E. Stinzianni, A. Cordes, P.Y. Hung, D.-H. Kim, R.J.W. Hill, W.Y. Loh, C. Hobbs, “Ultra Low Contact Resistivity (<1×10-8 Ω-cm2) to In0.53Ga0.47As Fin Sidewalls (110)/(100) Surfaces: Realized with a VLSI Processed III-V Fin TLM Structure fabricated with III-V on Si Substrates,” International Electron Device Meeting (IEDM), San Francisco CA, USA, Dec 15 – 17, 2014

  • 43: Rinus T.P. Lee, R.J.W Hill, W-Y Loh, R-H Baek, S. Deora, K. Matthews, C. Huffman, K. Majumdar, T. Michalak, C. Borst, P.Y. Hung, C-H Chen, J-H Yum, T-W Kim, C.Y. Kang, W-E Wang, D-H Kim, C. Hobbs, P.D. Kirsch, “VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module,” International Electron Device Meeting (IEDM), Washington, DC, USA, December 9 – 11, 2013

  • 42: H Rusty Harris, Derek W Johnson, Richard J.W. Hill, Ed Piner, Man Hoi Wong, Rinus T.P. Lee, “High Voltage GaN Technology in a Silicon CMOS Environment: Challenges and Opportunities,” 224th ECS Meeting, San Francisco, CA, Oct 2 – Nov 1, 2013

  • 41: H. Fariborzi, Fred Chen, R. Nathanael, I-R. Chen, L. Hutin, R. Lee, T.-J. K. Liu, “Relays do not leak – CMOS does,” 50th Design Automation Conference (DAC), Austin, TX, USA, May 29 – June 7, 2013

  • 40: T-W Kim, D-H Kim, D-H Koh, RJW Hill, Rinus T.P. Lee, Man Hoi Wong, T. Cunningham, Jesús A Del Alamo, Sanjay Kumar Banerjee, S. Oktyabrsky, A. Greene, Y. Ohsawa, Y. Trickett, G. Nakamura, Qiang Li, Kei May Lau, C. Hobbs, Paul D Kirsch, Raj Jammy, “ETB-QW InAs MOSFET with scaled body for improved electrostatics,” International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 13, 2012

  • 39: (Invited) C.Y. Kang, K.W. Ang, R. Hill, W.Y. Loh, J Oh, R. Lee, David Gilmer, Gennadi Bersuker, C. Hobbs, Paul Kirsch, Klaus Hummler, S. Arkalgud, Raj Jammy, “Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world,” IEEE International Conference on IC Design & Technology (ICICDT), Austin, TX, USA, May 30 – Jun 1, 2012 

  • 38: (Invited) R. J. W. Hill, W.Y. Loh, J. Huang, T. Kim, R. Lee, W.E. Wang, J. Oh, C. Hobbs, P. D. Kirsch, R. Jammy, “Integration Challenges of III-V Materials in Advanced CMOS Logic,” 221st ECS Meeting. Seattle, Washington, May 6-10, 2012

  • 37: I-Ru Chen, Louis Hutin, Chanro Park, Rinus Lee, Rhesa Nathanael, Jack Yaung, Jaeseok Jeon, Tsu-Jae King Liu, “Scaled micro-relay structure with low strain gradient for reduced operating voltage,” 221st ECS Meeting. Seattle, Washington, May 6-10, 2012

  • 36: (Invited) P.D. Kirsch, R.J.W Hill, J Huang, W.Y. Loh, T-W Kim, M.H. Wong, B.G. Min, C. Huffman, D. Veksler, C.D. Young, K.W. Ang, I. Ali, R.T.P. Lee, T. Ngai, A. Wang, W-E Wang, T.H. Cunningham, Y.T. Chen, P.Y. Hung, E. Bersch, B. Sassman, M. Cruz, S. Trammell, R. Droopad, S. Oktybrysky, J.C. Lee, G. Bersuker, C. Hobbs, R. Jammy, “Challenges of III–V materials in advanced CMOS logic,” VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 23 – 25, 2012

  • 35: Shao Ming Koh, Wei-Jing Zhou, Rinus T.P. Lee, Mantavya Sinha, Chee-Mang Ng, Zhiyong Zhao, Helen Maynard, Naushad Variam, Yuri Erokhin, Ganesh Samudra, Yee-Chia Yeo, “Silicon-Carbon source/drain stressors: Integration of a novel nickel aluminide-silicide and post-solid-phase-epitaxy anneal for reduced Schottky-barrier and leakage,” 216th ECS Meeting, Vienna, Austria, October 4 – 9, 2009

  • 34: (Invited) Yee-Chia Yeo, Rinus T.P. Lee, “Advanced Contact Technology for MOSFETs: Integration of New Materials for Series Resistance Reduction,” 216th ECS Meeting, Vienna, Austria, October 4 – 9, 2009

  • 33: Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo, “Single silicide comprising Nickel-Dysprosium alloy for integration in p-and n-FinFETs with independent control of contact resistance by Aluminum implant,” Symposium on VLSI Technology, Honolulu, HI, USA,  June 16-18, 2009

  • 32: R.T.P. Lee, D.Z. Chi, and Y.C. Yeo, “Sulfur segregation at the platinum silicide: silicon:carbon interface for electron barrier height reduction: An approach to enable independent control of contact resistances for n- and p-channel FinFETs with a single metal silicide,” European MRS Spring Meeting, Strasbourg, France, June 8 – 12, 2009

  • 31: Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo, “Integration of Al segregated NiSiGe/SiGe source/drain contact technology in p-FinFETs for drive current enhancement,” 215th ECS Meeting, San Francisco, CA, May 24 – 29, 2009

  • 30: Mantavya Sinha, Rinus T.P. Lee, Sivasubramaniam Nandini Devi, Guo-Qiang Lo, Eng Fong Chor, Yee-Chia Yeo, “p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction,” VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 27 – 29, 2009

  • 29: P. S. Y. Lim, R. T. P. Lee, A. E. J. Lim, A. T. Y. Koh, M. Sinha, D. Z. Chi, Y. C. Yeo, “Schottky-Barrier Height Tuning of Nickel Silicide on Epitaxial Silicon-Carbon Films with High Substitutional Carbon Content,” International Conference on
    Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 23-26, 2008


  • 28: Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Ben L-H Tan, Ganesh S. Samudra, N Balasubramanian, Yee-Chia Yeo, “5 nm gate length nanowire-FETs and planar UTB-FETs with pure germanium source/drain stressors and laser-free melt-enhanced dopant (MeltED) diffusion and activation technique,” Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008

  • 27: Rinus Tek-Po Lee, Alvin Tian-Yi Koh, Wei-Wei Fang, Kian-Ming Tan, Andy Eu-Jin Lim, Tsung-Yang Liow, Chow Shue-Yin, Anna M Yong, Hoong Shing Wong, Guo-Qiang Lo, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance,” Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008

  • 26: Hoong-Shing Wong, Fang-Yue Liu, Kah-Wee Ang, Shao-Ming Koh, Alvin Tian-Yi Koh, Tsung-Yang Liow, Rinus Tek-Po Lee, Andy Eu-Jin Lim, Wei-Wei Fang, Ming Zhu, Lap Chan, N Balasubramaniam, Ganesh Samudra, Yee-Chia Yeo, “Selenium Co-implantation and segregation as a new contact technology for nanoscale SOI N-FETs featuring NiSi: C formed on silicon-carbon (Si:C) source/drain stressors,” Symposium on VLSI Technology, Honolulu, HI, USA, June 17 – 19, 2008

  • 25: Tsung-Yang Liow, Kian-Ming Tan, Doran Weeks, Rinus T.P. Lee, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, M Bauer, Jennifer Spear, Shawn G Thomas, Ganesh S. Samudra, N Balasubramanian, Yee-Chia Yeo, “Strained FinFETs with In-situ Doped Si 1-y C y Source and Drain Stressors: Performance Boost with Lateral Stressor Encroachment and High Substitutional Carbon Content,” VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr 21 – 23, 2008

  • 24: Hoong-Shing Wong, Alvin Tian-Yi Koh, Hock-Chun Chin, Rinus Tek-Po Lee, Lap Chan, Ganesh Samudra, Yee-Chia Yeo, “A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors,” VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 21 – 23, 2008

  • 23: Lina Wei-Wei Fang, Ji-Sheng Pan, Andy Eu-Jin Lim, Rinus Tek-Po Lee, Minghua Li, Rong Zhao, Luping Shi, Tow-Chong Chong, Yee-Chia Yeo, “Photoemission Study of Energy Band Alignment of Ge2Sb2Te5 and Common CMOS Materials,” MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008

  • 22: R.T.P. Lee, F.Y. Liu, K.M. Tan, A.E.-J. Lim, T.Y. Liow, S. Tripathy, G.S. Samudra, D.Z. Chi, and Y.C. Yeo, “Formation of nickel-based germanosilicide contacts on silicon-germanium-tin (Si1-x-yGexSny) source/drain stressors,” MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008

  • 21: G.H. Wang, E.-H. Toh, R.T.P. Lee, X.-C. Wang, D.H.L. Seng, S. Tripathy, Y.- L. Foo, G. Samudra, and Y.-C. Yeo, “Contact technology for germanium-tin (GeSn) source/drain using nickel and nickel-platinum alloys,” MRS Spring Meeting, San Francisco, CA, USA, March 24 – 28, 2008

  • 20: Rinus Tek Po Lee, Kian-Ming Tan, Tsung-Yang Liow, Andy Eu-Jin Lim, Guo-Qiang Lo, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs,” MRS Spring Meeting, San Francisco, CA, USA, April 9 – 13, 2007

  • 19: Andy Eu-Jin Lim, Wei-Wei Fang, Fangyue Liu, Rinus T.P. Lee, Ganesh S Samudra, Dim-Lee Kwong, Yee-Chia Yeo, “Interface dipole mechanism and NMOS Ni-FUSI gate work function engineering using rare-earth metal (RE)-based dielectric interlayers,” International Semiconductor Device Research Symposium (ISDRS), Maryland, MD, Dec  12 – 14, 2007

  • 18: Kian-Ming Tan, Ming Zhu, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Keat Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo, “A New Liner Stressor with Very High Intrinsic Stress (≫ 6 GPa) and Low Permittivity Comprising Diamond-Like Carbon (DLC) for Strained P-Channel Transistors,” International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 12, 2007

  • 17: Rinus Tek-Po Lee, Alvin Tian-Yi Koh, Fang-Yue Liu, Wei-Wei Fang, Tsung-Yang Liow, Kian-Ming Tan, Poh-Chong Lim, Andy Eu-Jin Lim, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, Guo-Qiang Lo, Xincai Wang, David Kuang-Yong Low, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Route to low parasitic resistance in MuGFETs with silicon-carbon source/drain: Integration of novel low barrier Ni(M)Si:C metal silicides and pulsed laser annealing,” International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 10 – 12, 2007

  • 16: Tsung-Yang Liow, R.T.P Lee, K.M. Tan, M. Zhu, K.M. Hoe, G.S. Samudra, N Balasubramanian, Y.C. Yeo, “Strained n-channel FinFETs with high-stress nickel silicide-carbon contacts and integration with FUSI metal gate technology,” International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 18 – 21, 2007

  • 15: R.T.P. Lee, K.M. Tan, A. E.-J. Lim, T.Y. Liow, X.C. Chen, M. Zhu, A.T.Y. Koh,
    K.M. Hoe, S.Y. Chow, G.Q. Lo, G.S. Samudra, D.Z. Chi, Y.C. Yeo, “Contact technology
    employing nickel-platinum germanosilicide alloys for p-channel FinFETs with silicon-germanium source and drain stressors,” International Conference on Solid State Devices and Materials (SSDM), Ibaraki, Japan, September 18 – 21, 2007


  • 14: Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Keat-Mun Hoe, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo, “Strain enhancement in spacerless N-channel FinFETs with silicon-carbon source and drain stressors,” 37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 11 – 13, 2007

  • 13: Andy Eu-Jin Lim, Rinus TP Lee, Xin Peng Wang, Wan Sik Hwang, Chih-Hang Tung, Doreen MY Lai, Ganesh Samudra, Dim-Lee Kwong, Yee-Chia Yeo, “Band edge NMOS work function for nickel fully-silicided (FUSI) gate obtained by the insertion of novel Y-, Tb-, and Yb-based interlayers,” 37th European Solid State Device Research Conference (ESSDERC), Munich, Germany, September 11 – 13, 2007

  • 12: Rinus TP Lee, Tsung-Yang Liow, Kian-Ming Tan, Andy Eu-Jin Lim, Chee-Seng Ho, Keat-Mum Hoe, M.Y. Lai, Thomas Osipowicz, Guo-Qiang Lo, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Novel epitaxial nickel aluminide-silicide with low Schottky-barrier and series resistance for enhanced performance of dopant-segregated source/drain N-channel MuGFETs,” Symposium on VLSI Technology, Kyoto, Japan, June 12 – 16, 2007

  • 11: Rinus Tek Po Lee, Li-Tao Yang, Kah-Wee Ang, Tsung-Yang Liow, Kian-Ming Tan, Andrew See-Weng Wong, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Material and Electrical Characterization of Nickel Silicide-Carbon as Contact Metal to Silicon-Carbon Source and Drain Stressors,” MRS Spring Meeting, San Francisco, CA, USA, April 9 – 13, 2007

  • 10: Tsung-Yang Liow, Kian-Ming Tan, Hock-Chun Chin, Rinus T.P. Lee, Chih-Hang Tung, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo, “Carrier transport characteristics of sub-30 nm strained n-channel FinFETs featuring silicon-carbon source/drain regions and methods for further performance enhancement,” International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 11 – 13, 2006

  • 09: Rinus T.P. Lee, Tsung-Yang Liow, Kian-Ming Tan, Andy Eu-Jin Lim, Hoong-Shing Wong, Poh-Chong Lim, Doreen MY Lai, Guo-Qiang Lo, Chih-Hang Tung, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Novel nickel-alloy silicides for source/drain contact resistance reduction in n-channel multiple-gate transistors with sub-35nm gate length,” International Electron Device Meeting (IEDM), San Francisco, CA, USA, Dec 11 – 13, 2006

  • 08: K.M. Tan, T.Y. Liow, R.T.P. Lee, K.J. Chui, C.H. Tung, N. Balasubramanian, G.S. Samudra, W.J. Yoo, Y.C. Yeo, “Sub-30 nm strained p-channel FinFETs with condensed SiGe source/drain stressors,” International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 12 – 15, 2006

  • 07: R.T.P. Lee, K.M. Tan, A.E-J Lim, T.Y. Liow, G.Q. Lo, G. Samudra, D.Z. Chi, Y.C. Yeo, “Sub-30 nm P-channel Schottky Source/Drain FinFETs: Integration of Pt3Si FUSI Metal Gate and High-k Dielectric,” International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, September 12 – 15, 2006

  • 06: T-Y Liow, K-M Tan, R. Lee, Anyan Du, C-H Tung, G Samudra, W-J Yoo, N Balasubramanian, Y-C Yeo, “Strained n-channel FinFETs with 25 nm gate length and silicon-carbon source/drain regions for performance enhancement,” Symposium on VLSI Technology, Honolulu, HI, USA, June 13 – 17, 2006

  • 05: H.B. Yao, C.C. Tan, S.L. Liew, C.T. Chua, C.K. Chua, R. Li, R.T.P. Lee, S.J. Lee, D.Z. Chi, “Material and electrical characterization of Ni-and Pt-germanides for p-channel germanium Schottky source/drain transistors,” International Workshop on Junction Technology (IWJT), Shanghai, China, May 15 – 16, 2006

  • 04: Rinus Tek Po Lee, Tsung-Yang Liow, Kian-Ming Tan, Kah-Wee Ang, King-Jien Chui, Qiang-Lo Guo, Ganesh Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Process-induced strained p-MOSFET featuring nickel-platinum silicided source/drain,” MRS Spring Meeting, San Francisco, CA, USA, April 17 – 21, 2006

  • 03: R.T.P. Lee, S.L. Liew, B Balakrishnan, K.Y. Lee, Y.C. Yeo, D.Z. Chi, “Material and Electrical Characterization of Nickel Germanide for p-channel Germanium Schottky Source/Drain Transistors,” International Conference on Solid State Devices and Materials (SSDM), Kobe, Japan, September 12 – 15, 2005

  • 02: (Invited) D.Z. Chi, R.T.P. Lee, S.J. Chua, “Addressing materials and process-integration issues of NiSi silicide process using impurity engineering,” International Workshop on Junction Technology (IWJT), Shanghai, China, March 16, 2004

  • 01: R.T.P. Lee, D.Z. Chi, S.J. Chua, “NiSi formation in the Ni (Ti)/SiO2/Si System,” MRS Spring Meeting, San Francisco, CA, USA, March 12 – 16, 2004