Patents

PATENTS

  • 27: Semiconductor devices with low resistance gate structures, US 11145716, Oct 12, 2021 |PDF| Lee Rinus Tek Po, Jiehui Shu
  • 26: Multiple threshold voltage devices, US11094598, Aug 17, 2021 |PDF| Bharat V Krishnan, Lee Rinus Tek Po, Jiehui Shu, Hyung Yoon Choi.
  • 25: Mask-free methods of forming structures in a semiconductor device, US11004953, May 11, 2021 |PDF| Lee Rinus Tek Po, Zang Hui, Jiehui Shu, Yu Hong, Hong Wei.
  • 24: Mask-free methods of forming structures in a semiconductor device, US10896853, Jan 19, 2021 |PDF| Jiehui Shu, Lee Rinus Tek Po, Hong Wei, Zang Hui, Yu Hong.
  • 23: Devices with highly active acceptor doping and method of production thereof, US10886178, Jan 5, 2021 |PDF| Lee Rinus Tek Po, Annie Levesque, Qun Gao, Hui Zang, Rishikesh Krishnan, Bharat Krishnan, Curtis Durfee
  • 22: Spacer structures for a transistor device, US10872979, Dec 22, 2020 |PDF| Hui Zang, Chung Foong Tang, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Lee Rinus Tek Po, Scott Beasor.
  • 21: Methods of forming spacers adjacent to a gate structures of a transistor device, US10629739, Apr 21, 2020 |PDF| Zang Hui, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong, Ruilong Xie, Lee Rinus Tek Po, Scott Beasor.
  • 20: Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array, US10418365, Sept 17, 2019 |PDF| Zang Hui, Ciavatti Jerome, Lee Rinus Tek Po.
  • 19: Common metal contact regions having different Schottky barrier heights and methods of manufacturing same, US10276683, Apr 30, 2019|PDF| Rinus Tek Po Lee, Jinping Liu, Ruilong Xie.
  • 18: Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor, US10263122, Apr 16, 2019 |PDF| Zang Hui, Xie Ruilong, Rinus Tek Po Lee, Lars Liebmann.
  • 17: Method for forming a protection device having an inner contact spacer and resulting devices, US10242982, Mar 26, 2019 |PDF| Xie Ruilong, Katsunori Onishi, Rinus Tek Po Lee.
  • 16: Vertical-transport transistors with self-aligned contacts, US10230000, Mar 12, 2019 |PDF|Emilie Bourjot, Daniel Chanemougame, Rinus Tek Po Lee, Xie Ruilong, Hui Zang.
  • 15: Microwave annealing of flowable oxides with trap layer, US10211045, Feb 19, 2019 |PDF| Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Rinus Tek Po Lee, Yiheng Xu.
  • 14: Methods, apparatus and system for vertical FinFET device with reduced parasitic capacitance, US10204904, Feb 12, 2019 |PDF| Zang Hui, Rinus Tek Po Lee.
  • 13: Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region, US10170544, Jan 1, 2019 |PDF|Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee.
  • 12: FinFETs with strained channels and reduced on state resistance, US10134876B2, Nov 20, 2018 |PDF| Bharat Krishnan, Timothy McArdle, Rinus Tek Po Lee, Shishir Ray, Akshey Sehgal.
  • 11: Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array, US10134739B1, Nov 20, 2018 |PDF| Zang Hui, Jerome Ciavatti, Rinus Tek Po Lee.
  • 10: Semiconductor structure including two-dimensional and three-dimensional bonding materials, US10121706, Nov 6, 2018 |PDF| Rinus T.P. Lee, Bharat Krishnan, Zang Hui, Matthew Stoker.
  • 09: Buried contact structures for a vertical field-effect transistor, US10109714B2 Oct 23, 2018 |PDF| Zang Hui, Rinus Tek Po Lee.
  • 08: Nanosheet FET with full dielectric isolation, US10103238B1, Oct 16, 2018 |PDF| Zang Hui, Rinus Tek Po Lee, Haigou Huang, Chanro Park, Ming Gyu Sung, Xie Ruilong.
  • 07: Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices, US9876077B1, Jan 23, 2018 |PDF| Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee.
  • 06: Buried contact structures for a vertical field-effect transistor, US9831317B1, Nov. 28, 2017 |PDF| Hui Zang, Tek Po Rinus Lee.
  • 05: Common metal contact regions having different Schottky barrier heights and methods of manufacturing same, US9812543B2, Nov 07, 2017|PDF| Rinus Tek Po Lee, Jinping Liu, Ruilong Xie.
  • 04: Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors, US9570552B1, Feb, 14, 2017 |PDF| Rinus Tek Po Lee, Jinping Liu.
  • 03: Metal alloy with an abrupt interface to III-V semiconductor, US8829567B2, Sept 9, 2014 |PDF| Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill.
  • 02: Silicide formed from ternary metal alloy films, US7335606B2, Feb 26, 2008 |PDF| Dongzhi Chi, Tek Po Rinus, Soo Jin Chua.
  • 01: Forming an electrical contact on an electronic component, US7015132B2, Mar 06, 2006 |PDF| Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah.

PATENT APPLICATIONS

  • 6: Asymmetric source/drain structures  structures in a semiconductor device, 16/676488, Nov 7, 2019. Jeff Shu, Baofu Zhu and Rinus Tek Po Lee.
  • 05: Semiconductor device having barrier layer made of two dimensional materials, 16/368,836, Mar 28, 2019. Rinus Tek Po Lee, Fuad Al-Amoody, Asli Sirman, Joseph Kassim, Zang Hui and Bharat Krishnan
  • 04: Rinus Tek Po Lee, Bharat V. Krishnan, Jinping Liu, Hui Zang, Judson Robert Holt, “Formation of band-edge contacts,” 15/352,963, November 16, 2016
  • 03: Rinus Lee, Wei-Yip Loh, Robert Tieckelmann, “N-type III-V semiconductor structures having ultra-shallow junctions and methods of forming same, ” US20150333128A1,  Nov 19, 2015
  • 02: Robert TIECKELMANN Wei-Yip Loh Rinus Tek Po Lee, “Phosphorus and arsenic doping of semiconductor materials,” US20150111372A1, April 23, 2015
  • 01: Dongzhi Chi, Ka Lee, Tek Po Lee, Siao Liew, Hai Yao, “Reliable Contacts,” US20070272955A1, Nov 29, 2007