ISSUED PATENTS
- 07: Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee, “Methods of Forming a Protection Layer on an Isolation Region of IC Products Comprising FinFET Devices,” US9,876,077, Jan 23, 2018
- 06: Hui Zang, Tek Po Rinus Lee, “Buried contact structures for a vertical field-effect transistor,” US9,831,317 B1, Nov. 28, 2017
- 05: Tek Po Rinus Lee, Jinping Liu, Ruilong Xie “Common metal contact regions having different Schottky barrier heights and methods of manufacturing same,” US9,812,543 B2, Nov. 07, 2017
- 04: Tek Po Rinus Lee, Jinping Liu, “Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors,” US9,570,552 B1, Feb, 14, 2017
- 03: Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill, “Metal alloy with an abrupt interface to III-V semiconductor,” US8,829,567, September 9, 2014
- 02: Dongzhi Chi, Tek Po Rinus, Soo Jin Chua, “Silicide formed from ternary metal alloy films,” US7,335,606, February 26, 2008
- 01: Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah, “Forming an electrical contact on an electronic component,” US7,015,132, March 06, 2006
PENDING PATENTS
- 13: Hui Zang, Chung Foong Tan, Guowei Xu, Haitaing Wang, Yue Zhong, Ruilong Xie, Tek Po Rinus Lee and Scott Beasor, “Methods of Forming Spacers Adjacent Gate Structures of a Transistor Device,” 16/038,384, July 18, 2018
- 12: Rishi Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard Jr. Rinus Tek Po Lee, Yiheng Xu, “Microwave Annealing of Flowable Oxides with Trap Layers,” 15/878,502, Jan 24, 2018
- 11: Hui Zang, Xie Ruilong, Rinus Tek Po Lee, Emile Bourjot and Daniel Chanemougame, “Vertical-Transport Transistors with Self-Aligned Contacts,” 15/671,605, August 8, 2017
- 10: Hui Zang, Jerome Ciavatti, Rinus Tek Po Lee, “Memory Array with Buried Bitlines below VFET Transistors of Memory Cells and Method of Forming the Memory Array,” 15/661,058, July 27, 2017
- 09: Zang Hui, Rinus Tek Po Lee, Haigou Huang, Chanro Park, Ming Gyu Sung, Xie Ruilong “Nanosheet FET with Full Dielectric Isolation,” 15/652,890, July 18, 2017
- 08: Zang Hui, Rinus Tek Po Lee, “Methods, Apparatus and System for Vertical FinFET Device with Reduced Parasitic Capacitance,” 15/592,172, May 10, 2017
- 07: Bharat Krishnan, Timothy McArdle, Rinus Tek Po Lee, Shishir Ray, Akshey Sehgal, “FinFETs with Strained Channels and Reduced on State Resistance,” 15/475,873, March 31, 2017
- 06: Xie Ruilong, Katsunori Onishi, Rinus Tek Po Lee, “Method for Forming a Protection Device Having an Inner Contact Spacer and Resulting Devices,” 15/455,313, March 10, 2017
- 05: Rinus Tek Po Lee, Bharat V. Krishnan, Hui Zang, Matthew Stoker, “Semiconductor Structure including Two-Dimensional and Three-Dimensional Bonding Materials,” 15/361,809, November 28, 2016
- 04: Rinus Tek Po Lee, Bharat V. Krishnan, Jinping Liu, Hui Zang, Judson Robert Holt, “Formation of Band-Edge Contacts,” 15/352,963, November 16, 2016
- 03: Rinus Lee, Wei-Yip Loh, Robert Tieckelmann, “N-type III-V semiconductor structures having ultra-shallow junctions and methods of forming same, ” US20150333128A1, Nov 19, 2015
- 02: Robert TIECKELMANN Wei-Yip Loh Rinus Tek Po Lee, “Phosphorus and arsenic doping of semiconductor materials,” US20150111372A1, April 23, 2015
- 01: Dongzhi Chi, Ka Lee, Tek Po Lee, Siao Liew, Hai Yao, “Reliable Contacts,” US20070272955A1, Nov 29, 2007
