ISSUED PATENTS
- 12: Bharat Krishnan, Timothy McArdle, Rinus Tek Po Lee, Shishir Ray, Akshey Sehgal, “FinFETs with strained channels and reduced on state resistance,” US10134876B2, Nov 20, 2018
- 11: Zang Hui, Jerome Ciavatti, Rinus Tek Po Lee, “Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array,” US10134739B1, Nov 20, 2018
- 10: Rinus T.P. Lee, Bharat Krishnan, Zang Hui, Matthew Stoker, “Semiconductor structure including two-dimensional and three-dimensional bonding materials,” US10121706, Nov 6, 2018
- 09: Zang Hui, Rinus Tek Po Lee, “Buried contact structures for a vertical field-effect transistor,” US10109714B2, Oct 23, 2018
- 08: Zang Hui, Rinus Tek Po Lee, Haigou Huang, Chanro Park, Ming Gyu Sung, Xie Ruilong “Nanosheet FET with full dielectric isolation,” US10103238B1, Oct 16, 2018
- 07: Xie Ruilong, Christopher Prindle, Ming Gyu Sung, Rinus Tek Po Lee, “Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices,” US9876,077, Jan 23, 2018
- 06: Hui Zang, Tek Po Rinus Lee, “Buried contact structures for a vertical field-effect transistor,” US9831317 B1, Nov. 28, 2017
- 05: Tek Po Rinus Lee, Jinping Liu, Ruilong Xie “Common metal contact regions having different Schottky barrier heights and methods of manufacturing same,” US9812543 B2, Nov. 07, 2017
- 04: Tek Po Rinus Lee, Jinping Liu, “Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors,” US9570552 B1, Feb, 14, 2017
- 03: Rinus Tek Po Lee, Tae Woo Kim, Man Hoi Wong, Richard Hill, “Metal alloy with an abrupt interface to III-V semiconductor,” US8829567, September 9, 2014
- 02: Dongzhi Chi, Tek Po Rinus, Soo Jin Chua, “Silicide formed from ternary metal alloy films,” US7335606, February 26, 2008
- 01: Syamal Kumar Lahiri, Rinus Tek Po Lee, Zuruzi Bin Abu Samah, “Forming an electrical contact on an electronic component,” US7015132, March 06, 2006
PENDING PATENTS
- 08: Hui Zang, Chung Foong Tan, Guowei Xu, Haitaing Wang, Yue Zhong, Ruilong Xie, Tek Po Rinus Lee and Scott Beasor, “Methods of forming spacers adjacent gate structures of a transistor device,” 16/038,384, July 18, 2018
- 07: Rishi Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard Jr. Rinus Tek Po Lee, Yiheng Xu, “Microwave annealing of flowable oxides with trap layers,” 15/878,502, Jan 24, 2018
- 10: Hui Zang, Xie Ruilong, Rinus Tek Po Lee, Emile Bourjot and Daniel Chanemougame, “Vertical-transport transistors with self-aligned contacts,” 15/671,605, August 8, 2017
- 06: Zang Hui, Rinus Tek Po Lee, “Methods, apparatus and system for vertical FinFET device with reduced parasitic capacitance,” 15/592,172, May 10, 2017
- 05: Xie Ruilong, Katsunori Onishi, Rinus Tek Po Lee, “Method for forming a protection device having an inner contact spacer and resulting devices,” 15/455,313, March 10, 2017
- 04: Rinus Tek Po Lee, Bharat V. Krishnan, Jinping Liu, Hui Zang, Judson Robert Holt, “Formation of band-edge contacts,” 15/352,963, November 16, 2016
- 03: Rinus Lee, Wei-Yip Loh, Robert Tieckelmann, “N-type III-V semiconductor structures having ultra-shallow junctions and methods of forming same, ” US20150333128A1, Nov 19, 2015
- 02: Robert TIECKELMANN Wei-Yip Loh Rinus Tek Po Lee, “Phosphorus and arsenic doping of semiconductor materials,” US20150111372A1, April 23, 2015
- 01: Dongzhi Chi, Ka Lee, Tek Po Lee, Siao Liew, Hai Yao, “Reliable Contacts,” US20070272955A1, Nov 29, 2007
