Journal Publications

  • 49: (Invited Review) A.P. Jacob, R. Xie, M.G. Sung, L. Liebmann, R.T.P. Lee, B. Taylor, “Scaling Challenges for Advanced CMOS Devices,” International Journal of High Speed Electronics and Systems 26, p. 1740001, 2017

  • 48: Lee A. Walsh, Conan Weiland, Anthony P. McCoy, Joseph C. Woicik, Rinus T.P. Lee, Pat Lysaght, Greg Hughes, “Investigation of the thermal stability of Mo-In0. 45Ga0. 47As for applications as source/drain contacts,” Journal of Applied Physics 120 (13), p. 135303, 2016

  • 47: Tommaso Orzali, Alexey Vert, Rinus T.P. Lee, Aras Norvilas, Gensheng Huang, Joshua L Herman, Richard J.W. Hill, Satyavolu S. Papa Rao, “Heavily tellurium doped n-type InGaAs grown by MOCVD on 300mm Si wafers,” Journal of Crystal Growth 426, pp. 243-247, 2015

  • 46: Lee A Walsh, Greg Hughes, Conan Weiland, Joseph C Woicik, Rinus TP Lee, Wei-Yip Loh, Pat Lysaght, Chris Hobbs, “Ni-(In, Ga) As alloy formation investigated by hard-X-ray photoelectron spectroscopy and X-ray absorption spectroscopy,” Physical Review Applied 2 (6), p. 064010, 2014

  • 45: M. Abraham, S.Y. Yu, W.H. Choi, R.T.P. Lee, S.E. Mohney, “Very low resistance alloyed Ni-based ohmic contacts to InP-capped and uncapped n+-In0. 53 Ga0. 47As,” Journal of Applied Physics 116 (16), p. 164506, 2014 

  • 44: Derek W. Johnson, Pradhyumna Ravikirthi, Jae Woo Suh, Rinus T.P. Lee, Richard J.W. Hill, Man Hoi Wong, Edwin L. Piner, Harlan Rusty Harris, “Challenges of contact module integration for GaN-based devices in a Si-CMOS environment,” Journal of Vacuum Science & Technology B 32 (3) p.030606, 2014

  • 43: (Invited Review) S. Deora, G. Bersuker, W-Y Loh, D. Veksler, K. Matthews, T.W. Kim, R.T.P. Lee, R.J.W. Hill, D-H Kim, W-E Wang, C Hobbs, P.D. Kirsch, “Positive bias instability and recovery in InGaAs channel nMOSFETs,” IEEE Transactions on Device and Materials Reliability 13 (4), pp. 507-514, 2013

  • 42: Derek W Johnson, Rinus T.P. Lee, Richard J.W. Hill, Man Hoi Wong, Gennadi Bersuker, Edwin L. Piner, Paul D. Kirsch, H. Rusty Harris, “Threshold voltage shift due to charge trapping in dielectric-gated AlGaN/GaN high electron mobility transistors examined in Au-free technology,” IEEE Transactions on Electron Devices 60 (10), pp. 3197-3203, 2013

  • 41: M. Sinha, R.T.P Lee, E.F. Chor, Y.C. Yeo, “Contact resistance reduction technology using aluminum implant and segregation for strained p-FinFETs with silicon–germanium source/drain,” IEEE Transactions on Electron Devices 57 (6), pp. 1279-1286, 2010

  • 40: M. Sinha, R.T.P. Lee, E.F. Chor, Y.C. Yeo, “Schottky barrier height modulation of Nickel–dysprosium-alloy germanosilicide contacts for strained P-FinFETs,” IEEE Electron Device Letters 30 (12), pp. 1278-1280, 2009

  • 39: R.T.P. Lee, A.T.Y. Koh, K.M. Tan, T.Y. Liow, D.Z. Chi, Y.C. Yeo, “The Role of Carbon and Dysprosium in Ni[Dy]Si:C Contacts for Schottky-Barrier Height Reduction and Application in N-Channel MOSFETs With Si:C Source/Drain Stressors,” IEEE Transactions on Electron Devices 56 (11), pp. 2770-2777, 2009

  • 38: Shao Ming Koh, Wei-Jing Zhou, Rinus T.P. Lee, Mantavya Sinha, Chee-Mang Ng, Zhiyong Zhao, Helen Maynard, Naushad Variam, Yuri Erokhin, Ganesh Samudra, Yee-Chia Yeo, “Silicon: Carbon source/drain stressors: Integration of a novel nickel aluminide-silicide and post-solid-phase-epitaxy anneal for reduced Schottky-barrier and leakage,” ECS Transactions 25 (7), pp. 211-216, 2009

  • 37: P.S.Y. Lim, R.T.P. Lee, M. Sinha, D.Z. Chi, Y.C. Yeo, “Effect of substitutional carbon concentration on Schottky-barrier height of nickel silicide formed on epitaxial silicon-carbon films,” Journal of Applied Physics 106 (4), p. 043703, 2009

  • 36: R.T.P. Lee, D.Z. Chi, Y.C. Yeo, “Platinum Germanosilicide as Source/Drain Contacts in P-Channel Fin Field-Effect Transistors (FinFETs),” IEEE Transactions on Electron Devices 56 (7), pp. 1458-1465, 2009

  • 35: K.M. Tan, M. Yang, T.Y. Liow, R.T.P. Lee, Y.C. Yeo, “Ultra high-stress liner comprising diamond-like carbon for performance enhancement of p-channel multiple-gate transistors,” IEEE Transactions on Electron Devices 56 (6), pp. 1277-1283, 2009

  • 34: M Sinha, RTP Lee, SN Devi, GQ Lo, EF Chor, YC Yeo, “Integration of Al segregated NiSiGe/SiGe source/drain contact technology in p-FinFETs for drive current enhancement,” ECS Transactions 19 (1), pp. 323-330, 2009

  • 33: R.T.P. Lee, A.E.J. Lim, K.M. Tan, T.Y. Liow, D.Z. Chi, Y.C. Yeo, “Sulfur-induced PtSi: C/Si: C Schottky barrier height lowering for realizing n-channel FinFETs with reduced external resistance,” IEEE Electron Device Letters 30 (5), pp. 472-474, 2009

  • 32: M. Sinha, R.T.P. Lee, A. Lohani, S. Mhaisalkar, E.F. Chor, Y.C. Yeo, “Achieving sub-0.1 eV hole Schottky barrier height for NiSiGe on SiGe by aluminum segregation,” Journal of The Electrochemical Society 156 (4), pp. H233-H238, 2009

  • 31: K.M. Tan, M. Yang, W.W. Fang, A.E.J. Lim, R.T.P. Lee, T.Y. Liow, Y.C. Yeo, “Performance benefits of diamond-like carbon liner stressor in strained p-channel field-effect transistors with silicon–germanium source and drain,” IEEE Electron Device Letters 30 (3), pp. 250-253, 2009

  • 30: M. Sinha, R.T.P. Lee, K.M. Tan, G.Q. Lo, E.F. Chor, Y.C. Yeo, “Novel Aluminum Segregation at NiSi/p+-Si Source/Drain Contact for Drive Current Enhancement in P-Channel FinFETs,” IEEE Electron Device Letters 30 (1), pp. 85-87, 2009

  • 29: Tsung-Yang Liow, Kian-Ming Tan, Rinus Tek Po Lee, Ming Zhu, Ben Lian-Huat Tan, N Balasubramanian, Yee-Chia Yeo, “Strained silicon nanowire transistors with germanium source and drain stressors,” IEEE Transactions on Electron Devices 55 (11), pp. 3048-3055, 2008

  • 28: Tsung-Yang Liow, Kian-Ming Tan, Doran Weeks, Rinus Tek Po Lee, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, Matthias Bauer, Jennifer Spear, Shawn G Thomas, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo, “Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon (Si1−yCy) Source and Drain Stressors With High Carbon Content,” IEEE Transactions on Electron Devices 55 (9), pp. 2475-2483, 2008

  • 27: A.E.J. Lim, R.T.P. Lee, G.S. Samudra, D.L. Kwong, Y.C. Yeo, “Novel rare-earth dielectric interlayers for wide NMOS work-function tunability in Ni-FUSI gates,” IEEE Transactions on Electron Devices 55 (9), pp. 2370-2377, 2008

  • 26: Andy Eu-Jin Lim, Rinus Tek Po Lee, Ganesh S Samudra, Dim-Lee Kwong, Yee-Chia Yeo, “Modification of Molybdenum Gate Electrode Work Function via (La-, Al-Induced) Dipole Effect at High-k/SiO2 Interface,” IEEE Electron Device Letters 29 (8), pp. 848-851, 2008

  • 25: Kian-Ming Tan, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Narayanan Balasubramanian, Yee-Chia Yeo, “Diamond-like carbon (DLC) liner: A new stressor for p-channel multiple-gate field-effect transistors,” IEEE Electron Device Letters 29 (7), pp. 750-752, 2008

  • 24: Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Ming Zhu, Ben L-H Tan, N Balasubramanian, Yee-Chia Yeo, “Germanium source and drain stressors for ultrathin-body and nanowire field-effect transistors,” IEEE Electron Device Letters 29 (7), pp. 808-810, 2008

  • 23: Alvin Tian-Yi Koh, Rinus Tek-Po Lee, Fang-Yue Liu, Tsung-Yang Liow, Kian Ming Tan, Xincai Wang, Ganesh S Samudra, N Balasubramanian, Dong-Zhi Chi, Yee-Chia Yeo, “Pulsed laser annealing of silicon-carbon source/drain in MuGFETs for enhanced dopant activation and high substitutional carbon concentration,” IEEE Electron Device Letters 29 (5), pp. 464-467, 2008

  • 22: R.T.P. Lee, K.M. Tan, A.E.J. Lim, T.Y. Liow, G.S. Samudra, D.Z. Chi, Y.C. Yeo, “P-Channel Tri-Gate FinFETs Featuring Ni1−yPty SiGe Source/Drain Contacts for Enhanced Drive Current Performance,” IEEE Electron Device Letters 29 (5), pp. 438-441, 2008

  • 21: A.E.J. Lim, R.T.P. Lee, A.T.Y. Koh, G.S. Samudra, D.L. Kwong, Y.C. Yeo, “Effectiveness of aluminum incorporation in nickel silicide and nickel germanide metal gates for work function reduction,” Japanese Journal of Applied Physics 47 (4S), p. 2383, 2008

  • 20: Kian-Ming Tan, Tsung-Yang Liow, Rinus T.P. Lee, Ming Zhu, Keat-Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo, “Novel Extended-Pi Shaped Silicon–Germanium Source/Drain Stressors for Strain and Performance Enhancement in p-Channel Tri-Gate Fin-Type Field-Effect Transistor,” Japanese Journal of Applied Physics 47 (4S), p.2589, 2008

  • 19: Rinus Tek-Po Lee, Tsung-Yang Liow, Kian-Ming Tan, Andy Eu-Jin Lim, Alvin Tian-Yi Koh, Ming Zhu, Guo-Qiang Lo, Ganesh S. Samudra, Dong Zhi Chi, Yee-Chia Yeo, “Achieving conduction band-edge Schottky barrier height for arsenic-segregated nickel aluminide disilicide and implementation in FinFETs with ultra-narrow fin widths,” IEEE Electron Device Letters 29 (4), pp. 382-385, 2008

  • 18: Alvin Tian-Yi Koh, Rinus Tek-Po Lee, Andy Eu-Jin Lim, Doreen Mei-Ying Lai, Dong-Zhi Chi, Keat-Mun Hoe, N. Balasubramanian, Ganesh S. Samudra, Yee-Chia Yeo, “Nickel-aluminum alloy silicides with high aluminum content for contact resistance reduction and integration in n-channel field-effect transistors,”  Journal of The Electrochemical Society 155 (3), pp. H151-H155, 2008

  • 17: Kian-Ming Tan, Ming Zhu, Wei-Wei Fang, Mingchu Yang, Tsung-Yang Liow, Rinus T.P. Lee, Keat Mun Hoe, Chih-Hang Tung, Narayanan Balasubramanian, Ganesh S. Samudra, Yee-Chia Yeo, “A high-stress liner comprising diamond-like carbon (DLC) for strained p-channel MOSFET,” IEEE Electron Device Letters 29 (2), 192-194, 2008

  • 16: Tsung-Yang Liow, Kian-Ming Tan, Rinus TP Lee, Ming Zhu, Keat-Mun Hoe, Ganesh S Samudra, N Balasubramanian, Yee-Chia Yeo, “Spacer removal technique for boosting strain in n-channel FinFETs with silicon-carbon source and drain stressors,” IEEE Electron Device Letters 29 (1), pp. 80-82, 2008

  • 15: Rinus TP Lee, Li-Tao Yang, Tsung-Yang Liow, Kian-Ming Tan, Andy Eu-Jin Lim, Kah-Wee Ang, Doreen Mei Ying Lai, Keat Mun Hoe, Guo-Qiang Lo, Ganesh S. Samudra, Dong Zhi Chi, Yee-Chia Yeo, “Nickel-silicide: carbon contact technology for n-channel MOSFETs with silicon–carbon source/drain,” IEEE Electron Device Letters 29 (1), pp. 89-92, 2008

  • 14: Tsung-Yang Liow, Kian-Ming Tan, Rinus T.P. Lee, Chih-Hang Tung, Ganesh S. Samudra, N. Balasubramanian, Yee-Chia Yeo, “N-channel (110)-sidewall strained FinFETs with silicon–carbon source and drain stressors and tensile capping layer,” IEEE Electron Device Letters 28 (11), 1014-1017, 2007

     

  • 13: A.E.J. Lim, W.W. Fang, F. Liu, R.T.P. Lee, G. Samudra, D.L. Kwong, Y.C. Yeo, “Impact of interfacial dipole on effective work function of nickel fully silicided gate electrodes formed on rare-earth-based dielectric interlayers,” Applied Physics Letters 91 (17), p172115, 2007

  • 12: Kian-Ming Tan, Tsung-Yang Liow, Rinus TP Lee, Keat Mun Hoe, Chih-Hang Tung, N Balasubramanian, Ganesh S Samudra, Yee-Chia Yeo, “Strained p-Channel FinFETs With Extended Π Shaped Silicon–Germanium Source and Drain Stressors,”  IEEE Electron Device Letters 28 (10), 905-908, 2007

  • 11: D.Z. Chi, R.T.P. Lee, A.S.W. Wong, “Addressing materials and integration issues for NiSi silicide contact metallization in nano-scale CMOS devices,” Thin Solid Films 515 (22), 8102-8108, 2007

  • 10: Rinus Tek-Po Lee, Kian-Ming Tan, Tsung-Yang Liow, Chee-Sheng Ho, S Tripathy, Ganesh S Samudra, Dong-Zhi Chi, Yee-Chia Yeo, “Probing the ErSi1. 7 phase formation by micro-Raman spectroscopy,” Journal of The Electrochemical Society 154 (5), pp. H361-H364, 2007

  • 09: Rinus TP Lee, Andy Eu-Jin Lim, Kian-Ming Tan, Tsung-Yang Liow, Guo-Qiang Lo, Ganesh S Samudra, Dong Zhi Chi, Yee-Chia Yeo, “N-channel FinFETs with 25-nm gate length and Schottky-barrier source and drain featuring ytterbium silicide,” IEEE Electron Device Letters 28 (2), pp. 164-167, 2007

  • 08: A.E.J. Lim, R.T.P. Lee, X.P. Wang, W.S. Hwang, C.H. Tung, G.S. Samudra, D.L. Kwong, Y.C. Yeo, “Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET,” IEEE Electron Device Letters 28 (6), pp. 482-485, 2007

  • 07: K.M. Tan, T.Y. Liow, R.T.P. Lee, C.H. Tung, G.S. Samudra, W.J. Yoo, Y.C. Yeo, “Drive-current enhancement in FinFETs using gate-induced stress,” IEEE Electron Device Letters 27 (9), pp. 769-771, 2006

  • 06: S.L. Liew, R.T.P. Lee, K.Y. Lee, B. Balakrisnan, S.Y. Chow, M.Y. Lai, D.Z. Chi, “Enhanced morphological stability of NiGe films formed using Ni (Zr) alloy,” Thin Solid Films 504 (1), pp. 104-107, 2006

  • 05: A.E.J. Lim, R.T.P. Lee, C.H. Tung, S. Tripathy, D.L. Kwong, Y.C. Yeo, “Semiconductor Devices, Materials, and Processing-Full Silicidation of Silicon Gate Electrodes Using Nickel-Terbium Alloy for MOSFET Applications,” Journal of the Electrochemical Society 153 (4), p.G337, 2006

  • 04: R.T.P. Lee, S.L. Liew, W.D. Wang, E.K.C. Chua, S.Y. Chow, M.Y. Lai, D.Z. Chi, “Fully Silicided Ni1− x Pt x Si Metal Gate Electrode for p-MOSFETs,” Electrochemical and Solid-State Letters 8 (7), pp. G156-G159, 2005

  • 03: D.Z. Chi, R.T.P. Lee, S.J. Chua, S.J. Lee, S. Ashok, D.L. Kwong, “Current–voltage characteristics of Schottky barriers with barrier heights larger than the semiconductor band gap: The case of Ni Ge∕ n-(001) Ge contact,” Journal of Applied Physics 97 (11), p. 113706, 2005

  • 02: R.T.P. Lee, D.Z. Chi, M.Y. Lai, N.L. Yakovlev, S.J. Chua, “Effects of Ti incorporation in Ni on silicidation reaction and structural/electrical properties of NiSi,” Journal of The Electrochemical Society 151 (9), pp. G642-G647, 2004

  • 01: R.T.P. Lee, D.Z. Chi, S.J. Chua, “Maskless Process for Fabrication of Ultra-Fine Pitch Solder Bumps for Flip Chip Interconnects,” J. Electronic Packaging 125 (4), pp. 597-601, 2003